373 lines
12 KiB
Verilog
373 lines
12 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_gtlb (
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// pll clocks & resets
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input qpll_ref_clk,
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input cpll_ref_clk,
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output qpll0_rst,
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output qpll0_ref_clk_in,
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output cpll_rst_m_0,
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output cpll_ref_clk_in_0,
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// channel interface (rx)
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input rx_p,
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input rx_n,
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input [ 3:0] rx_gt_charisk_0,
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input [ 3:0] rx_gt_disperr_0,
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input [ 3:0] rx_gt_notintable_0,
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input [31:0] rx_gt_data_0,
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output reg rx_gt_comma_align_enb_0,
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output rx_0_p,
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output rx_0_n,
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input rx_rst_0,
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output rx_rst_m_0,
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input rx_pll_rst_0,
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input rx_gt_rst_0,
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output rx_gt_rst_m_0,
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input rx_pll_locked_0,
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output rx_pll_locked_m_0,
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input rx_user_ready_0,
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output rx_user_ready_m_0,
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input rx_rst_done_0,
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output rx_rst_done_m_0,
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input rx_out_clk_0,
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output rx_clk_0,
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output rx_sysref_0,
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input rx_sync_0,
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input rx_sof_0,
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input [31:0] rx_data_0,
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input rx_ip_rst_0,
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output [ 3:0] rx_ip_sof_0,
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output [31:0] rx_ip_data_0,
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input rx_ip_sysref_0,
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output rx_ip_sync_0,
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input rx_ip_rst_done_0,
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// channel interface (tx)
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output tx_p,
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output tx_n,
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output [ 3:0] tx_gt_charisk_0,
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output reg [31:0] tx_gt_data_0,
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input tx_0_p,
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input tx_0_n,
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input tx_rst_0,
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output tx_rst_m_0,
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input tx_pll_rst_0,
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input tx_gt_rst_0,
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output tx_gt_rst_m_0,
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input tx_pll_locked_0,
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output tx_pll_locked_m_0,
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input tx_user_ready_0,
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output tx_user_ready_m_0,
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input tx_rst_done_0,
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output tx_rst_done_m_0,
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input tx_out_clk_0,
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output tx_clk_0,
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output tx_sysref_0,
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output tx_sync_0,
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output [31:0] tx_data_0,
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input tx_ip_rst_0,
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input [31:0] tx_ip_data_0,
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input tx_ip_sysref_0,
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input tx_ip_sync_0,
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input tx_ip_rst_done_0,
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// up interface
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input up_clk,
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input up_rstn,
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input up_pn_err_clr,
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input up_pn_oos_clr,
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output reg up_pn_err,
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output reg up_pn_oos);
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// internal registers
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reg tx_sync_m1 = 'd0;
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reg tx_sync_m2 = 'd0;
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reg tx_sync = 'd0;
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reg [31:0] tx_pn_data = 'd0;
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reg tx_charisk_1 = 'd0;
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reg [ 3:0] rx_kcount = 'd0;
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reg rx_sync = 'd0;
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reg [31:0] rx_pn_data = 'd0;
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reg rx_pn_match_d = 'd0;
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reg rx_pn_match_z = 'd0;
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reg rx_pn_err = 'd0;
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reg rx_pn_oos = 'd0;
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reg [ 3:0] rx_pn_oos_count = 'd0;
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reg up_pn_err_clr_d = 'd0;
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reg up_pn_oos_clr_d = 'd0;
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// internal signals
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wire [31:0] rx_gt_data_0_s;
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wire [31:0] rx_pn_data_s;
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wire rx_pn_match_d_s;
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wire rx_pn_match_z_s;
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wire rx_pn_match_s;
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wire rx_pn_update_s;
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wire rx_pn_err_s;
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wire up_pn_err_s;
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wire up_pn_oos_s;
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// pn31 function
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function [31:0] pn31;
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input [31:0] din;
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reg [31:0] dout;
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begin
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dout[31] = din[31] ^ din[28];
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dout[30] = din[30] ^ din[27];
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dout[29] = din[29] ^ din[26];
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dout[28] = din[28] ^ din[25];
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dout[27] = din[27] ^ din[24];
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dout[26] = din[26] ^ din[23];
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dout[25] = din[25] ^ din[22];
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dout[24] = din[24] ^ din[21];
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dout[23] = din[23] ^ din[20];
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dout[22] = din[22] ^ din[19];
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dout[21] = din[21] ^ din[18];
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dout[20] = din[20] ^ din[17];
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dout[19] = din[19] ^ din[16];
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dout[18] = din[18] ^ din[15];
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dout[17] = din[17] ^ din[14];
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dout[16] = din[16] ^ din[13];
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dout[15] = din[15] ^ din[12];
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dout[14] = din[14] ^ din[11];
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dout[13] = din[13] ^ din[10];
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dout[12] = din[12] ^ din[ 9];
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dout[11] = din[11] ^ din[ 8];
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dout[10] = din[10] ^ din[ 7];
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dout[ 9] = din[ 9] ^ din[ 6];
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dout[ 8] = din[ 8] ^ din[ 5];
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dout[ 7] = din[ 7] ^ din[ 4];
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dout[ 6] = din[ 6] ^ din[ 3];
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dout[ 5] = din[ 5] ^ din[ 2];
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dout[ 4] = din[ 4] ^ din[ 1];
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dout[ 3] = din[ 3] ^ din[ 0];
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dout[ 2] = din[ 2] ^ din[31] ^ din[28];
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dout[ 1] = din[ 1] ^ din[30] ^ din[27];
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dout[ 0] = din[ 0] ^ din[29] ^ din[26];
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pn31 = dout;
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end
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endfunction
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// defaults
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assign qpll0_rst = tx_pll_rst_0 | rx_pll_rst_0;
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assign qpll0_ref_clk_in = qpll_ref_clk;
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assign cpll_rst_m_0 = tx_pll_rst_0 | rx_pll_rst_0;
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assign cpll_ref_clk_in_0 = cpll_ref_clk;
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assign rx_0_p = rx_p;
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assign rx_0_n = rx_n;
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assign rx_rst_m_0 = rx_rst_0;
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assign rx_gt_rst_m_0 = rx_gt_rst_0;
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assign rx_pll_locked_m_0 = rx_pll_locked_0;
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assign rx_user_ready_m_0 = rx_user_ready_0;
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assign rx_rst_done_m_0 = & rx_rst_done_0;
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assign rx_clk_0 = rx_out_clk_0;
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assign rx_sysref_0 = 1'd0;
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assign rx_ip_sof_0 = 4'hf;
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assign rx_ip_data_0 = 32'd0;
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assign rx_ip_sync_0 = rx_sync;
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assign tx_p = tx_0_p;
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assign tx_n = tx_0_n;
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assign tx_rst_m_0 = tx_rst_0;
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assign tx_gt_rst_m_0 = tx_gt_rst_0;
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assign tx_pll_locked_m_0 = tx_pll_locked_0;
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assign tx_user_ready_m_0 = tx_user_ready_0;
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assign tx_rst_done_m_0 = tx_rst_done_0;
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assign tx_clk_0 = tx_out_clk_0;
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assign tx_sysref_0 = 1'd0;
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assign tx_sync_0 = tx_sync;
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assign tx_data_0 = 32'd0;
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// gt loop back
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assign tx_gt_charisk_0 = {4{tx_charisk_1}};
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always @(posedge tx_out_clk_0 or posedge tx_rst_0) begin
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if (tx_rst_0 == 1'b1) begin
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tx_sync_m1 <= 1'd0;
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tx_sync_m2 <= 1'd0;
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tx_sync <= 1'd0;
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tx_pn_data <= 32'hffffffff;
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tx_charisk_1 <= 1'd0;
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tx_gt_data_0 <= 32'd0;
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end else begin
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tx_sync_m1 <= rx_sync;
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tx_sync_m2 <= tx_sync_m1;
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tx_sync <= tx_sync_m2;
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tx_pn_data <= pn31(tx_pn_data);
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if (tx_sync == 1'b1) begin
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tx_charisk_1 <= 1'd0;
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tx_gt_data_0[31:24] <= tx_pn_data[ 7: 0];
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tx_gt_data_0[23:16] <= tx_pn_data[15: 8];
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tx_gt_data_0[15: 8] <= tx_pn_data[23:16];
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tx_gt_data_0[ 7: 0] <= tx_pn_data[31:24];
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end else begin
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tx_charisk_1 <= 1'd1;
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tx_gt_data_0[31:24] <= 8'hbc;
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tx_gt_data_0[23:16] <= 8'hbc;
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tx_gt_data_0[15: 8] <= 8'hbc;
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tx_gt_data_0[ 7: 0] <= 8'hbc;
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end
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end
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end
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assign rx_gt_data_0_s[31:24] = rx_gt_data_0[ 7: 0];
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assign rx_gt_data_0_s[23:16] = rx_gt_data_0[15: 8];
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assign rx_gt_data_0_s[15: 8] = rx_gt_data_0[23:16];
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assign rx_gt_data_0_s[ 7: 0] = rx_gt_data_0[31:24];
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always @(posedge rx_out_clk_0 or posedge rx_rst_0) begin
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if (rx_rst_0 == 1'b1) begin
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rx_gt_comma_align_enb_0 <= 1'd0;
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rx_kcount <= 4'd0;
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rx_sync <= 1'd0;
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end else begin
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rx_gt_comma_align_enb_0 <= ~rx_sync;
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if ((rx_gt_disperr_0 == 0) && (rx_gt_notintable_0 == 0)) begin
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if ((rx_gt_charisk_0 == 4'hf) && (rx_gt_data_0_s == 32'hbcbcbcbc)) begin
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rx_kcount <= rx_kcount + 1'b1;
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if (rx_kcount == 4'hf) begin
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rx_sync <= 1'b1;
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end
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end else begin
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rx_kcount <= 4'd0;
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rx_sync <= rx_sync;
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end
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end else begin
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rx_kcount <= 4'd0;
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rx_sync <= 1'd0;
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end
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end
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end
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assign rx_pn_data_s = (rx_pn_oos == 1'b1) ? rx_gt_data_0_s : rx_pn_data;
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assign rx_pn_match_d_s = (rx_gt_data_0_s == rx_pn_data) ? 1'b1 : 1'b0;
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assign rx_pn_match_z_s = (rx_gt_data_0_s == 'd0) ? 1'b0 : 1'b1;
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assign rx_pn_match_s = rx_pn_match_d & rx_pn_match_z;
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assign rx_pn_update_s = ~(rx_pn_oos ^ rx_pn_match_s);
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assign rx_pn_err_s = ~(rx_pn_oos | rx_pn_match_s);
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always @(posedge rx_out_clk_0 or posedge rx_rst_0) begin
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if (rx_rst_0 == 1'b1) begin
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rx_pn_data <= 32'd0;
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rx_pn_match_d <= 'd0;
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rx_pn_match_z <= 'd0;
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rx_pn_err <= 'd0;
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rx_pn_oos <= 'd0;
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rx_pn_oos_count <= 'd0;
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end else begin
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rx_pn_data <= pn31(rx_pn_data_s);
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rx_pn_match_d <= rx_pn_match_d_s;
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rx_pn_match_z <= rx_pn_match_z_s;
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if ((rx_gt_disperr_0 == 0) && (rx_gt_notintable_0 == 0) && (rx_gt_charisk_0 == 0)) begin
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rx_pn_err <= rx_pn_err_s;
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if ((rx_pn_update_s == 1'b1) && (rx_pn_oos_count >= 15)) begin
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rx_pn_oos <= ~rx_pn_oos;
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end
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if (rx_pn_update_s == 1'b1) begin
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rx_pn_oos_count <= rx_pn_oos_count + 1'b1;
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end else begin
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rx_pn_oos_count <= 'd0;
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end
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end else begin
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rx_pn_err <= 1'd0;
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rx_pn_oos <= 1'd1;
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rx_pn_oos_count <= 'd0;
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end
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end
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end
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// up clock
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up_xfer_status #(.DATA_WIDTH(2)) i_xfer_status (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_data_status ({up_pn_err_s, up_pn_oos_s}),
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.d_rst (rx_rst_0),
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.d_clk (rx_out_clk_0),
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.d_data_status ({rx_pn_err, rx_pn_oos}));
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always @(posedge up_clk or negedge up_rstn) begin
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if (up_rstn == 1'b0) begin
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up_pn_err_clr_d <= 'd0;
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up_pn_oos_clr_d <= 'd0;
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up_pn_err <= 'd0;
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up_pn_oos <= 'd0;
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end else begin
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up_pn_err_clr_d <= up_pn_err_clr;
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up_pn_oos_clr_d <= up_pn_oos_clr;
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if (up_pn_err_s == 1'b1) begin
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up_pn_err <= 1'b1;
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end else if ((up_pn_err_clr == 1'b1) &&
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(up_pn_err_clr_d == 1'b0)) begin
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up_pn_err <= 1'b0;
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end
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if (up_pn_oos_s == 1'b1) begin
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up_pn_oos <= 1'b1;
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end else if ((up_pn_oos_clr == 1'b1) &&
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(up_pn_oos_clr_d == 1'b0)) begin
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up_pn_oos <= 1'b0;
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end
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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