100 lines
3.4 KiB
Tcl
100 lines
3.4 KiB
Tcl
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package require qsys
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
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set_module_property NAME axi_adxcvr
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set_module_property DESCRIPTION "AXI ADXCVR Core"
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set_module_property VERSION 1.0
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set_module_property GROUP "Analog Devices"
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set_module_property DISPLAY_NAME axi_adxcvr
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set_module_property ELABORATION_CALLBACK p_axi_adxcvr
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# files
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add_fileset quartus_synth QUARTUS_SYNTH "" ""
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set_fileset_property quartus_synth TOP_LEVEL axi_adxcvr
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add_fileset_file up_axi.v VERILOG PATH $ad_hdl_dir/library/common/up_axi.v
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add_fileset_file axi_adxcvr_up.v VERILOG PATH axi_adxcvr_up.v
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add_fileset_file axi_adxcvr.v VERILOG PATH axi_adxcvr.v TOP_LEVEL_FILE
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# parameters
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add_parameter ID INTEGER 0
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set_parameter_property ID DISPLAY_NAME ID
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set_parameter_property ID TYPE INTEGER
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set_parameter_property ID UNITS None
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set_parameter_property ID HDL_PARAMETER true
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add_parameter TX_OR_RX_N INTEGER 0
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set_parameter_property TX_OR_RX_N DISPLAY_NAME TX_OR_RX_N
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set_parameter_property TX_OR_RX_N TYPE INTEGER
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set_parameter_property TX_OR_RX_N UNITS None
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set_parameter_property TX_OR_RX_N HDL_PARAMETER true
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add_parameter NUM_OF_LANES INTEGER 4
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set_parameter_property NUM_OF_LANES DISPLAY_NAME NUM_OF_LANES
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set_parameter_property NUM_OF_LANES TYPE INTEGER
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set_parameter_property NUM_OF_LANES UNITS None
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set_parameter_property NUM_OF_LANES HDL_PARAMETER true
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# axi4 slave interface
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add_interface s_axi_clock clock end
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add_interface_port s_axi_clock s_axi_aclk clk Input 1
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add_interface s_axi_reset reset end
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set_interface_property s_axi_reset associatedClock s_axi_clock
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add_interface_port s_axi_reset s_axi_aresetn reset_n Input 1
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add_interface s_axi axi4lite end
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set_interface_property s_axi associatedClock s_axi_clock
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set_interface_property s_axi associatedReset s_axi_reset
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add_interface_port s_axi s_axi_awvalid awvalid Input 1
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add_interface_port s_axi s_axi_awaddr awaddr Input 16
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add_interface_port s_axi s_axi_awprot awprot Input 3
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add_interface_port s_axi s_axi_awready awready Output 1
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add_interface_port s_axi s_axi_wvalid wvalid Input 1
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add_interface_port s_axi s_axi_wdata wdata Input 32
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add_interface_port s_axi s_axi_wstrb wstrb Input 4
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add_interface_port s_axi s_axi_wready wready Output 1
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add_interface_port s_axi s_axi_bvalid bvalid Output 1
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add_interface_port s_axi s_axi_bresp bresp Output 2
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add_interface_port s_axi s_axi_bready bready Input 1
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add_interface_port s_axi s_axi_arvalid arvalid Input 1
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add_interface_port s_axi s_axi_araddr araddr Input 16
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add_interface_port s_axi s_axi_arprot arprot Input 3
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add_interface_port s_axi s_axi_arready arready Output 1
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add_interface_port s_axi s_axi_rvalid rvalid Output 1
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add_interface_port s_axi s_axi_rresp rresp Output 2
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add_interface_port s_axi s_axi_rdata rdata Output 32
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add_interface_port s_axi s_axi_rready rready Input 1
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# xcvr interface
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ad_alt_intf reset up_rst output 1 s_axi_clock
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set_interface_property if_up_rst associatedResetSinks s_axi_reset
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add_interface core_pll_locked conduit end
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add_interface_port core_pll_locked up_pll_locked export Input 1
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# name changes
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proc p_axi_adxcvr {} {
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set m_tx_or_rx_n [get_parameter_value TX_OR_RX_N]
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set m_num_of_lanes [get_parameter_value NUM_OF_LANES]
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if {$m_tx_or_rx_n == 1} {
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add_interface ready conduit end
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add_interface_port ready up_ready tx_ready input $m_num_of_lanes
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}
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if {$m_tx_or_rx_n == 0} {
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add_interface ready conduit end
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add_interface_port ready up_ready rx_ready input $m_num_of_lanes
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}
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}
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