283 lines
8.1 KiB
Verilog
Executable File
283 lines
8.1 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad6676 #(
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parameter ID = 0,
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parameter DEVICE_TYPE = 0,
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parameter IO_DELAY_GROUP = "adc_if_delay_group") (
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// jesd interface
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// rx_clk is (line-rate/40)
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input rx_clk,
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input [ 3:0] rx_sof,
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input rx_valid,
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output rx_ready,
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input [63:0] rx_data,
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// dma interface
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output adc_clk,
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output adc_rst,
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output adc_valid_0,
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output adc_enable_0,
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output [31:0] adc_data_0,
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output adc_valid_1,
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output adc_enable_1,
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output [31:0] adc_data_1,
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input adc_dovf,
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input adc_dunf,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [31:0] s_axi_awaddr,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [31:0] s_axi_araddr,
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output s_axi_arready,
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output s_axi_rvalid,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready,
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input [ 2:0] s_axi_awprot,
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input [ 2:0] s_axi_arprot);
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// internal registers
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reg up_status_pn_err = 'd0;
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reg up_status_pn_oos = 'd0;
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reg up_status_or = 'd0;
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reg [31:0] up_rdata = 'd0;
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reg up_rack = 'd0;
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reg up_wack = 'd0;
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// internal clocks & resets
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wire up_rstn;
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wire up_clk;
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// internal signals
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wire [31:0] adc_data_0_s;
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wire [31:0] adc_data_1_s;
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wire adc_or_a_s;
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wire adc_or_b_s;
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wire adc_status_s;
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wire [ 1:0] up_status_pn_err_s;
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wire [ 1:0] up_status_pn_oos_s;
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wire [ 1:0] up_status_or_s;
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wire [31:0] up_rdata_s[0:2];
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wire up_rack_s[0:2];
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wire up_wack_s[0:2];
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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// signal name changes
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assign up_clk = s_axi_aclk;
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assign up_rstn = s_axi_aresetn;
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assign rx_ready = 1'b1;
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// processor read interface
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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up_status_pn_err <= 'd0;
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up_status_pn_oos <= 'd0;
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up_status_or <= 'd0;
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up_rdata <= 'd0;
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up_rack <= 'd0;
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up_wack <= 'd0;
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end else begin
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up_status_pn_err <= | up_status_pn_err_s;
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up_status_pn_oos <= | up_status_pn_oos_s;
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up_status_or <= | up_status_or_s;
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up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2];
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up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2];
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up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2];
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end
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end
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// adc valid
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assign adc_valid_0 = 1'b1;
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assign adc_valid_1 = 1'b1;
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// main (device interface)
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axi_ad6676_if #(.DEVICE_TYPE (DEVICE_TYPE)) i_if (
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.rx_clk (rx_clk),
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.rx_sof (rx_sof),
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.rx_data (rx_data),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_data_a (adc_data_0_s),
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.adc_data_b (adc_data_1_s),
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.adc_or_a (adc_or_a_s),
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.adc_or_b (adc_or_b_s),
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.adc_status (adc_status_s));
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// channel
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axi_ad6676_channel #(.Q_OR_I_N(0), .CHANNEL_ID(0)) i_channel_0 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_data (adc_data_0_s),
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.adc_or (adc_or_a_s),
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.adc_dfmt_data (adc_data_0),
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.adc_enable (adc_enable_0),
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.up_adc_pn_err (up_status_pn_err_s[0]),
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.up_adc_pn_oos (up_status_pn_oos_s[0]),
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.up_adc_or (up_status_or_s[0]),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[0]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[0]),
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.up_rack (up_rack_s[0]));
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// channel
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axi_ad6676_channel #(.Q_OR_I_N(1), .CHANNEL_ID(1)) i_channel_1 (
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_data (adc_data_1_s),
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.adc_or (adc_or_b_s),
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.adc_dfmt_data (adc_data_1),
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.adc_enable (adc_enable_1),
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.up_adc_pn_err (up_status_pn_err_s[1]),
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.up_adc_pn_oos (up_status_pn_oos_s[1]),
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.up_adc_or (up_status_or_s[1]),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[1]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[1]),
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.up_rack (up_rack_s[1]));
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// common processor control
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up_adc_common #(.ID(ID)) i_up_adc_common (
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.mmcm_rst (),
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.adc_clk (adc_clk),
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.adc_rst (adc_rst),
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.adc_r1_mode (),
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.adc_ddr_edgesel (),
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.adc_pin_mode (),
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.adc_status (adc_status_s),
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.adc_sync_status (1'd0),
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.adc_status_ovf (adc_dovf),
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.adc_status_unf (adc_dunf),
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.adc_clk_ratio (32'd1),
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.adc_start_code (),
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.adc_sref_sync (),
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.adc_sync (),
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.up_adc_ce (),
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.up_status_pn_err (up_status_pn_err),
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.up_status_pn_oos (up_status_pn_oos),
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.up_status_or (up_status_or),
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.up_drp_sel (),
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.up_drp_wr (),
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.up_drp_addr (),
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.up_drp_wdata (),
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.up_drp_rdata (32'd0),
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.up_drp_ready (1'd0),
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.up_drp_locked (1'd1),
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.up_usr_chanmax_out (),
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.up_usr_chanmax_in (8'd1),
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.up_adc_gpio_in (32'd0),
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.up_adc_gpio_out (),
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[2]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[2]),
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.up_rack (up_rack_s[2]));
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// up bus interface
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up_axi i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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