728 lines
24 KiB
ReStructuredText
728 lines
24 KiB
ReStructuredText
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.. _template_project:
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Project template
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================================================================================
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Overview
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-------------------------------------------------------------------------------
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**\*Some specifications about the board, the chip, etc. Typically the
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information found on the** https://www.analog.com/en/products/
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**website**\ \*
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Supported boards
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-------------------------------------------------------------------------------
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**\*IF IT APPLIES**\ \*
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- :adi:`AD9081-FMCA-EBZ <EVAL-AD9081>`
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- :adi:`AD9082-FMCA-EBZ <EVAL-AD9082>`
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Supported devices
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-------------------------------------------------------------------------------
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**\*EXAMPLES**\ \*
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- :adi:`AD9081`
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- :adi:`AD9177`
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- :adi:`AD9209`
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Supported carriers
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-------------------------------------------------------------------------------
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**\*At least one. Should be updated each time the project is ported to
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another carrier. Take these tables as an example:**\ \*
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.. list-table::
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:widths: 35 35 30
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:header-rows: 1
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* - Evaluation board
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- Carrier
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- FMC slot
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* - :adi:`AD9081-FMCA-EBZ <EVAL-AD9081>`
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- `A10SoC`_
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- FMCA
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* -
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- :xilinx:`VCK190`
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- FMC0
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* -
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- :xilinx:`VCU118`
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- FMC+
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* -
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- :xilinx:`VCU128`
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- FMC+
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* -
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- :xilinx:`ZCU102`
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- FMC HPC0
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* -
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- :xilinx:`ZC706`
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- FMC HPC
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.. list-table::
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:widths: 35 35 30
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:header-rows: 1
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* - Evaluation board
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- Carrier
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- FMC slot
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* - :adi:`AD9082-FMCA-EBZ <EVAL-AD9082>`
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- :xilinx:`VCK190`
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- FMC0
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* -
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- :xilinx:`VCU118`
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- FMC+
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* -
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- :xilinx:`ZCU102`
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- FMC HPC0
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* -
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- :xilinx:`ZC706`
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- FMC HPC
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Block design
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-------------------------------------------------------------------------------
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Block diagram
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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\**\* MUST HAVE \**\* The data path and clock domains are depicted in
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the below diagram:
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\*\* TIP: upload the .svg file for the diagram to have high quality \*\*
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If the project has multiple ways of configuration, then make subsections to
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this section and show the default configuration and some other popular modes.
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.. image:: ../images/ad9783_ebz/ad9783_zcu102_block_diagram.svg
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:width: 800
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:align: center
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:alt: AD9783-EBZ/ZCU102 block diagram
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Configuration modes
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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\**\* MENTION IF ANY MODES ARE AVAILABLE FOR CONFIGURATION \**\*
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**EXAMPLES BUT NOT LIMITED TO**
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The following are the parameters of this project that can be configured:
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- JESD_MODE: used link layer encoder mode
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- 64B66B - 64b66b link layer defined in JESD204C, uses AMD IP as Physical
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Layer
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- 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical
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Layer
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- RX_LANE_RATE: lane rate of the Rx link (MxFE to FPGA)
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- TX_LANE_RATE: lane rate of the Tx link (FPGA to MxFE)
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- REF_CLK_RATE: the rate of the reference clock
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- [RX/TX]_JESD_M: number of converters per link
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- [RX/TX]_JESD_L: number of lanes per link
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- [RX/TX]_JESD_S: number of samples per frame
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- [RX/TX]_JESD_NP: number of bits per sample
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- [RX/TX]_NUM_LINKS: number of links
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- [RX/TX]_TPL_WIDTH
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- TDD_SUPPORT: set to 1, adds the TDD; enables external synchronization through TDD. Must be set to 1 when SHARED_DEVCLK=1
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- SHARED_DEVCLK
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- TDD_CHANNEL_CNT
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- TDD_SYNC_WIDTH
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- TDD_SYNC_INT
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- TDD_SYNC_EXT
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- TDD_SYNC_EXT_CDC: if enabled, the CDC circuitry for the external sync signal is added
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- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in
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kilosamples per converter (M)
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- [ADC/DAC]_DO_MEM_TYPE
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- Check out this guide on more details regarding these parameters:
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:dokuwiki:`resources/fpga/docs/axi_tdd`
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Clock scheme
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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- External clock source
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:dokuwiki:`AD-SYNCHRONA14-EBZ <resources/eval/user-guides/ad-synchrona14-ebz>`
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- SYSREF clocks are LVDS
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- ADCCLK and REFCLK are LVPECL
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\*\* ADD IMAGE IF APPLIES! TIP: upload the .svg file for the diagram to have
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high quality \*\*
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**\*DESCRIBE OTHER COMPONENTS FROM THE PROJECT, EX: SYNCHRONA**\ \*
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Only the channels presented in the clocking selection are relevant. For
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the rest, you can either disable them or just put a divided frequency of
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the source clock.
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Limitations
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^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
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**\*EXAMPLE OF CONFIGURATION/LIMITATION. PLEASE WRITE THIS KIND OF
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INFORMATION IF IT APPLIES TO THE PROJECT**\ \*
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The design has one JESD receive chain with 4 lanes at rate of 13Gbps.
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The JESD receive chain consists of a physical layer represented by an
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XCVR module, a link layer represented by an RX JESD LINK module and
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transport layer represented by a RX JESD TPL module. The link operates
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in Subclass 1.
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The link is set for full bandwidth mode and operate with the following
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parameters:
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Deframer paramaters: L=4, M=2, F=1, S=1, NP=16
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| SYSREF - 5.078125 MHZ
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| REFCLK - 325MHz (Lane Rate/40)
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| DEVICECLK - 325 MHz
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| ADCCLK - 1300MHz
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| JESD204B Lane Rate - 13Gbps
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The transport layer component presents on its output 128 bits at once on
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every clock cycle, representing 4 samples per converter. The two receive
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chains are merged together and transferred to the DDR with a single DMA.
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CPU/Memory interconnects addresses
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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The addresses are dependent on the architecture of the FPGA, having an offset
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added to the base address from HDL (see more at :ref:`architecture`).
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**If there are any PL SPI connections, they must be added in this table too**
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\**\* THIS IS JUST AN EXAMPLE \**\*
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Depending on the values of parameters $INTF_CFG, $ADI_PHY_SEL and $TDD_SUPPORT,
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some IPs are instatiated and some are not.
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Check-out the table below to find out the conditions.
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==================== ================================= =============== =========== ============
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Instance Depends on parameter Zynq/Microblaze ZynqMP Versal
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==================== ================================= =============== =========== ============
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axi_mxfe_rx_xcvr $INTF_CFG!="TX" & $ADI_PHY_SEL==1 0x44A6_0000 0x84A6_0000 0xA4A6_00000
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rx_mxfe_tpl_core $INTF_CFG!="TX" 0x44A1_0000 0x84A1_0000 0xA4A1_00000
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axi_mxfe_rx_jesd $INTF_CFG!="TX" 0x44A9_0000 0x84A9_0000 0xA4A9_00000
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axi_mxfe_rx_dma $INTF_CFG!="TX" 0x7C42_0000 0x9C42_0000 0xBC42_00000
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mxfe_rx_data_offload $INTF_CFG!="TX" 0x7C45_0000 0x9C45_0000 0xBC45_00000
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axi_mxfe_tx_xcvr $INTF_CFG!="RX" & $ADI_PHY_SEL==1 0x44B6_0000 0x84B6_0000 0xA4B6_00000
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tx_mxfe_tpl_core $INTF_CFG!="RX" 0x44B1_0000 0x84B1_0000 0xA4B1_00000
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axi_mxfe_tx_jesd $INTF_CFG!="RX" 0x44B9_0000 0x84B9_0000 0xA4B9_00000
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axi_mxfe_tx_dma $INTF_CFG!="RX" 0x7C43_0000 0x9C43_0000 0xBC43_00000
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mxfe_tx_data_offload $INTF_CFG!="RX" 0x7C44_0000 0x9C44_0000 0xBC44_00000
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axi_tdd_0 $TDD_SUPPORT==1 0x7C46_0000 0x9C46_0000 0xBC46_00000
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==================== ================================= =============== =========== ============
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I2C connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. list-table::
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:widths: 20 20 20 20 20
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:header-rows: 1
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* - I2C type
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- I2C manager instance
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- Alias
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- Address
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- I2C subordinate
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* -
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-
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-
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-
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-
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SPI connections
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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THESE ARE JUST EXAMPLES!!!
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USE WHICHEVER FITS BEST YOUR CASE
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.. list-table::
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:widths: 25 25 25 25
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:header-rows: 1
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* - SPI type
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- SPI manager instance
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- SPI subordinate
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- CS
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* - PS
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- SPI 0
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- ADXYZT
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- 0
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* - PS
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- SPI 1
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- AD0000
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- 0
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* - PL
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- axi_spi_bus_1
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- AD23456
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- 0
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GPIOs
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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**Add explanation depending on your case**
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.. list-table::
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:widths: 25 20 20 20 15
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:header-rows: 2
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* - GPIO signal
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- Direction
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- HDL GPIO EMIO
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- Software GPIO
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- Software GPIO
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* -
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- (from FPGA view)
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-
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- Zynq-7000
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- Zynq MP
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* - signal name
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- IN/OUT/INOUT
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- 32-63
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- 86-117
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- 110-141
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* - signal name
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- IN/OUT/INOUT
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- 64-95
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- 118-149
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- 142-173
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* - signal name
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- IN/OUT/INOUT
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- 96-127
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- 150-181
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- 174-205
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Interrupts
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Below are the Programmable Logic interrupts used in this project.
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You have many ways of writing this table: as a list-table or really to draw
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it. Take a look in the .rst of this page to see how they're written and
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which suits best your case.
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.. list-table::
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:widths: 30 10 15 15 15 15
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:header-rows: 1
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* - Instance name
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- HDL
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- Linux Zynq
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- Actual Zynq
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- Linux ZynqMP
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- Actual ZynqMP
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* - ---
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- 15
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- 59
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- 91
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- 111
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- 143
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* - ---
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- 14
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- 58
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- 90
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- 110
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- 142
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* - ---
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- 13
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- 57
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- 89
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- 109
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- 141
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* - ---
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- 12
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- 56
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- 88
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- 108
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- 140
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* - ---
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- 11
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- 55
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- 87
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- 107
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- 139
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* - ---
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- 10
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- 54
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- 86
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- 106
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- 138
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* - ---
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- 9
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- 53
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- 85
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- 105
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- 137
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* - ---
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- 8
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- 52
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- 84
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- 104
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- 136
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* - ---
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- 7
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- 36
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- 68
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- 96
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- 128
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* - ---
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- 6
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- 35
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- 67
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- 95
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- 127
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* - ---
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- 5
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- 34
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- 66
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- 94
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- 126
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* - ---
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- 4
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- 33
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- 65
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- 93
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- 125
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* - ---
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- 3
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- 32
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- 64
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- 92
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- 124
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* - ---
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- 2
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- 31
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- 63
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- 91
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- 123
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* - ---
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- 1
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- 30
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- 62
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- 90
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- 122
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* - ---
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- 0
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- 29
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- 61
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- 89
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- 121
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================ === ========== =========== ============ ============= ====== =============== ================
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Instance name HDL Linux Zynq Actual Zynq Linux ZynqMP Actual ZynqMP S10SoC Linux Cyclone V Actual Cyclone V
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================ === ========== =========== ============ ============= ====== =============== ================
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--- 15 59 91 111 143 32 55 87
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--- 14 58 90 110 142 31 54 86
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--- 13 57 89 109 141 30 53 85
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--- 12 56 88 108 140 29 52 84
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--- 11 55 87 107 139 28 51 83
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--- 10 54 86 106 138 27 50 82
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--- 9 53 85 105 137 26 49 81
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--- 8 52 84 104 136 25 48 80
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--- 7 36 68 96 128 24 47 79
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--- 6 35 67 95 127 23 46 78
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--- 5 34 66 94 126 22 45 77
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--- 4 33 65 93 125 21 44 76
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--- 3 32 64 92 124 20 43 75
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--- 2 31 63 91 123 19 42 74
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--- 1 30 62 90 122 18 41 73
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--- 0 29 61 89 121 17 40 72
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================ === ========== =========== ============ ============= ====== =============== ================
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!!!! These are the project-specific interrupts (usually found in
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/project_name/common/Project_name_bd,tcl).
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Add the name of the component that uses that interrupt.
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Delete the dropdown section when you insert the table in your page
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NOTE THAT FOR ULTRASCALE\+ DEVICES, THE PS I2C IS NOT SUPPORTED IN LINUX!!
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ALWAYS USE PL I2C FOR THESE DESIGNS!!
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Building the HDL project
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-------------------------------------------------------------------------------
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**\*YOU CAN KEEP THE FIRST PARAGRAPH SINCE IT IS GENERIC**\ \*
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The design is built upon ADI's generic HDL reference design framework.
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ADI does not distribute the bit/elf files of these projects so they
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must be built from the sources available :git-hdl:`here <>`. To get
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the source you must
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`clone <https://git-scm.com/book/en/v2/Git-Basics-Getting-a-Git-Repository>`__
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the HDL repository.
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Then go to the **\*PROJECT LOCATION WITHIN HDL (EX:
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projects/ad9695/zcu102)**\ \* location and run the make command by
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typing in your command prompt:
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**Linux/Cygwin/WSL**
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**\*Say which is the default configuration that's built when running
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``make``, give examples of running with all parameters and also with
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just one. Say that it will create a folder with the name ... when
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running with the following parameters.**\ \*
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.. code-block::
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:linenos:
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:emphasize-lines: 2, 6
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user@analog:~$ cd hdl/projects/ad9081_fmca_ebz/zcu102
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// these are just examples of how to write the *make* command with parameters
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user@analog:~/hdl/projects/ad9081_fmca_ebz/zcu102$ make parameter1=value parameter2=value
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user@analog:~$ cd hdl/projects/ad9081_fmca_ebz/a10soc
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// these are just examples of how to write the *make* command with parameters
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user@analog:~/hdl/projects/ad9081_fmca_ebz/a10soc$ make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 TX_JESD_NP=16
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The following dropdowns contain tables with the parameters that can be used to
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configure this project, depending on the carrier used.
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Where a cell contains a --- (dash) it means that the parameter doesn't exist
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for that project (ad9081_fmca_ebz/carrier or ad9082_fmca_ebz/carrier).
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.. collapsible:: Default values of the ``make`` parameters for AD9082-FMCA-EBZ
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+-------------------+-----------------------------------------------+
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| Parameter | Default value of the parameters |
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| | depending on carrier |
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| +--------+--------+--------------+--------------+
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| | VCK190 | VCU118 | ZC706 | ZCU102 |
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+===================+========+========+==============+==============+
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| JESD_MODE | 64B66B | 8B10B | :red:`8B10B*`| :red:`8B10B*`|
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+-------------------+--------+--------+--------------+--------------+
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| RX_LANE_RATE | 24.75 | 15 | 10 | 15 |
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+-------------------+--------+--------+--------------+--------------+
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| TX_LANE_RATE | 24.75 | 15 | 10 | 15 |
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+-------------------+--------+--------+--------------+--------------+
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| REF_CLK_RATE | 375 | --- | --- | --- |
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+-------------------+--------+--------+--------------+--------------+
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| RX_JESD_M | 4 | 4 | 8 | 4 |
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+-------------------+--------+--------+--------------+--------------+
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| RX_JESD_L | 8 | 8 | 4 | 8 |
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+-------------------+--------+--------+--------------+--------------+
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| RX_JESD_S | 4 | 1 | 1 | 1 |
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+-------------------+--------+--------+--------------+--------------+
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| RX_JESD_NP | 12 | 16 | 16 | 16 |
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+-------------------+--------+--------+--------------+--------------+
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| RX_NUM_LINKS | 1 | 1 | 1 | 1 |
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+-------------------+--------+--------+--------------+--------------+
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| RX_TPL_WIDTH | --- | --- | --- | {} |
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+-------------------+--------+--------+--------------+--------------+
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| TX_JESD_M | 4 | 4 | 8 | 4 |
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+-------------------+--------+--------+--------------+--------------+
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| TX_JESD_L | 8 | 8 | 4 | 8 |
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+-------------------+--------+--------+--------------+--------------+
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| TX_JESD_S | 8 | 1 | 1 | 1 |
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+-------------------+--------+--------+--------------+--------------+
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| TX_JESD_NP | 12 | 16 | 16 | 16 |
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+-------------------+--------+--------+--------------+--------------+
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| TX_NUM_LINKS | 1 | 1 | 1 | 1 |
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+-------------------+--------+--------+--------------+--------------+
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| TX_TPL_WIDTH | --- | --- | --- | {} |
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+-------------------+--------+--------+--------------+--------------+
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| RX_KS_PER_CHANNEL | 64 | 64 | --- | --- |
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+-------------------+--------+--------+--------------+--------------+
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| TX_KS_PER_CHANNEL | 64 | 64 | --- | --- |
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+-------------------+--------+--------+--------------+--------------+
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|
.. warning::
|
|
|
|
``*`` --- for this carrier only the 8B10B mode is supported
|
|
|
|
The result of the build, if parameters were used, will be in a folder named
|
|
by the configuration used:
|
|
|
|
if the following command was run
|
|
|
|
``make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 TX_JESD_NP=16``
|
|
|
|
then the folder name will be:
|
|
|
|
``RXRATE2_5_TXRATE2_5_RXL8_RXM4_RXS1_RXNP16_TXL8_TXM4_TXS1_TXNP16``
|
|
because of truncation of some keywords so the name will not exceed the limits
|
|
of the Operating System (``JESD``, ``LANE``, etc. are removed) of 260
|
|
characters.
|
|
|
|
**\*KEEP THIS LINE TOO**\ \*
|
|
A more comprehensive build guide can be found in the :ref:`build_hdl` user guide.
|
|
|
|
Software considerations
|
|
-------------------------------------------------------------------------------
|
|
|
|
\**\* MENTION THESE \**\*
|
|
|
|
ADC - crossbar config \**\* THIS IS JUST AN EXAMPLE \**\*
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
Due to physical constraints, Rx lanes are reordered as described in the
|
|
following table.
|
|
|
|
e.g physical lane 2 from ADC connects to logical lane 7
|
|
from the FPGA. Therefore the crossbar from the device must be set
|
|
accordingly.
|
|
|
|
============ ===========================
|
|
ADC phy Lane FPGA Rx lane / Logical Lane
|
|
============ ===========================
|
|
0 2
|
|
1 0
|
|
2 7
|
|
3 6
|
|
4 5
|
|
5 4
|
|
6 3
|
|
7 1
|
|
============ ===========================
|
|
|
|
DAC - crossbar config \**\* THIS IS JUST AN EXAMPLE \**\*
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
Due to physical constraints, Tx lanes are reordered as described in the
|
|
following table:
|
|
|
|
e.g physical lane 2 from DAC connects to logical lane 7
|
|
from the FPGA. Therefore the crossbar from the device must be set
|
|
accordingly.
|
|
|
|
============ ===========================
|
|
DAC phy Lane FPGA Tx lane / Logical Lane
|
|
============ ===========================
|
|
0 0
|
|
1 2
|
|
2 7
|
|
3 6
|
|
4 1
|
|
5 5
|
|
6 4
|
|
7 3
|
|
============ ===========================
|
|
|
|
Resources
|
|
-------------------------------------------------------------------------------
|
|
|
|
Systems related
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
- Links to the Quick start guides, to the pages where the hardware changes are
|
|
specified in detail, etc. in the form of a table as the one below
|
|
|
|
**THIS IS JUST AN EXAMPLE**
|
|
|
|
- :dokuwiki:`[Wiki] AD9081 & AD9082 & AD9988 & AD9986 Prototyping Platform User Guide <resources/eval/user-guides/ad9081_fmca_ebz>`
|
|
- Here you can find all the quick start guides on wiki documentation:dokuwiki:`[Wiki] AD9081 Quick Start Guides <resources/eval/user-guides/ad9081_fmca_ebz/quickstart>`
|
|
|
|
Here you can find the quick start guides available for these evaluation boards:
|
|
|
|
.. list-table::
|
|
:widths: 20 10 20 20 20 10
|
|
:header-rows: 1
|
|
|
|
* - Evaluation board
|
|
- Zynq-7000
|
|
- Zynq UltraScale+ MP
|
|
- Microblaze
|
|
- Versal
|
|
- Arria 10
|
|
* - AD9081/AD9082-FMCA-EBZ
|
|
- :dokuwiki:`ZC706 <resources/eval/user-guides/ad9081_fmca_ebz/quickstart/zynq>`
|
|
- :dokuwiki:`ZCU102 <resources/eval/user-guides/ad9081_fmca_ebz/quickstart/zynqmp>`
|
|
- :dokuwiki:`VCU118 <resources/eval/user-guides/ad9081_fmca_ebz/quickstart/microblaze>`
|
|
- :dokuwiki:`VCK190/VMK180 <resources/eval/user-guides/ad9081_fmca_ebz/quickstart/versal>`
|
|
- :dokuwiki:`A10SoC <resources/eval/user-guides/ad9081/quickstart/a10soc>`
|
|
|
|
- Other relevant information
|
|
|
|
Hardware related
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
- Product datasheets:
|
|
|
|
- :adi:`AD9081`
|
|
- :adi:`AD9082`
|
|
- :adi:`AD9988`
|
|
- :adi:`AD9986`
|
|
- `UG-1578, Device User Guide <https://www.analog.com/media/en/technical-documentation/user-guides/ad9081-ad9082-ug-1578.pdf>`__
|
|
- `UG-1829, Evaluation Board User Guide <https://www.analog.com/media/en/technical-documentation/user-guides/ad9081-fmca-ebz-9082-fmca-ebz-ug-1829.pdf>`__
|
|
|
|
HDL related
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
- Link to the project source code
|
|
- Table like the one below. Must have as first IP (if it exists) the IP that
|
|
was created with this project (i.e., axi_ad9783). If there isn't, then to
|
|
be taken in the order they are written in the Makefile of the project,
|
|
stating the source code link in a column and the documentation link in
|
|
another column
|
|
- Other relevant information
|
|
|
|
**THIS IS JUST AN EXAMPLE**
|
|
|
|
- :git-hdl:`AD9081_FMCA_EBZ HDL project source code <projects/ad9081_fmca_ebz>`
|
|
- :git-hdl:`AD9082_FMCA_EBZ HDL project source code <projects/ad9082_fmca_ebz>`
|
|
|
|
.. list-table::
|
|
:widths: 30 35 35
|
|
:header-rows: 1
|
|
|
|
* - IP name
|
|
- Source code link
|
|
- Documentation link
|
|
* - AXI_DMAC
|
|
- :git-hdl:`library/axi_dmac`
|
|
- :ref:`here <axi_dmac>`
|
|
* - AXI_SYSID
|
|
- :git-hdl:`library/axi_sysid`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
|
|
* - SYSID_ROM
|
|
- :git-hdl:`library/sysid_rom`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_sysid>`
|
|
* - UTIL_CPACK2
|
|
- :git-hdl:`library/util_pack/util_cpack2`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/docs/util_cpack>`
|
|
* - UTIL_UPACK2
|
|
- :git-hdl:`library/util_pack/util_upack2`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/docs/util_upack>`
|
|
* - UTIL_ADXCVR for AMD
|
|
- :git-hdl:`library/xilinx/util_adxcvr`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/docs/util_xcvr>`
|
|
* - AXI_ADXCVR for Intel
|
|
- :git-hdl:`library/intel/axi_adxcvr`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_adxcvr>`
|
|
* - AXI_ADXCVR for AMD
|
|
- :git-hdl:`library/xilinx/axi_adxcvr`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/docs/axi_adxcvr>`
|
|
* - AXI_JESD204_RX
|
|
- :git-hdl:`library/jesd204/axi_jesd204_rx`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/peripherals/jesd204/axi_jesd204_rx>`
|
|
* - AXI_JESD204_TX
|
|
- :git-hdl:`library/jesd204/axi_jesd204_tx`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/peripherals/jesd204/axi_jesd204_tx>`
|
|
* - JESD204_TPL_ADC
|
|
- :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_adc`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/peripherals/jesd204/jesd204_tpl_adc>`
|
|
* - JESD204_TPL_DAC
|
|
- :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac`
|
|
- :dokuwiki:`[Wiki] <resources/fpga/peripherals/jesd204/jesd204_tpl_dac>`
|
|
|
|
- :dokuwiki:`[Wiki] Generic JESD204B block designs <resources/fpga/docs/hdl/generic_jesd_bds>`
|
|
- :dokuwiki:`[Wiki] JESD204B High-Speed Serial Interface Support <resources/fpga/peripherals/jesd204>`
|
|
|
|
Software related
|
|
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
|
|
|
**THIS IS JUST AN EXAMPLE**
|
|
|
|
- :dokuwiki:`[Wiki] AD9081-FMCA-EBZ Linux driver wiki page <resources/tools-software/linux-drivers/iio-mxfe/ad9081>`
|
|
|
|
If there is no Linux driver page, then insert a link to the code of the driver
|
|
and of the device tree.
|
|
|
|
- Python support (THIS IS JUST AN EXAMPLE):
|
|
|
|
- `AD9081 class documentation <https://analogdevicesinc.github.io/pyadi-iio/devices/adi.ad9081.html>`__
|
|
- `PyADI-IIO documentation <https://analogdevicesinc.github.io/pyadi-iio/>`__
|
|
|
|
.. include:: ../common/more_information.rst
|
|
|
|
.. include:: ../common/support.rst
|
|
|
|
.. _A10SoC: https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-sx.html
|