56 lines
1.6 KiB
Verilog
56 lines
1.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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module splitter (
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input clk,
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input resetn,
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input s_valid,
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output s_ready,
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output [NUM_M-1:0] m_valid,
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input [NUM_M-1:0] m_ready
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);
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parameter NUM_M = 2;
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reg [NUM_M-1:0] acked;
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assign s_ready = &(m_ready | acked);
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assign m_valid = s_valid ? ~acked : {NUM_M{1'b0}};
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always @(posedge clk)
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begin
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if (resetn == 1'b0) begin
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acked <= {NUM_M{1'b0}};
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end else begin
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if (s_valid & s_ready)
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acked <= {NUM_M{1'b0}};
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else
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acked <= acked | (m_ready & m_valid);
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end
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end
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endmodule
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