136 lines
4.2 KiB
Verilog
136 lines
4.2 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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// Color Space Conversion, adder. This is a simple adder, but had to be
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// pipe-lined for faster clock rates. The delay input is delay-matched to
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// the sum pipe-line stages
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`timescale 1ps/1ps
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module ad_csc_1_add #(
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parameter DELAY_DATA_WIDTH = 16) (
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// all signed
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input clk,
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input [24:0] data_1,
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input [24:0] data_2,
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input [24:0] data_3,
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input [24:0] data_4,
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output reg [ 7:0] data_p,
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// delay match
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input [DW:0] ddata_in,
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output reg [DW:0] ddata_out);
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localparam DW = DELAY_DATA_WIDTH - 1;
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// internal registers
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reg [DW:0] p1_ddata = 'd0;
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reg [24:0] p1_data_1 = 'd0;
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reg [24:0] p1_data_2 = 'd0;
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reg [24:0] p1_data_3 = 'd0;
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reg [24:0] p1_data_4 = 'd0;
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reg [DW:0] p2_ddata = 'd0;
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reg [24:0] p2_data_0 = 'd0;
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reg [24:0] p2_data_1 = 'd0;
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reg [DW:0] p3_ddata = 'd0;
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reg [24:0] p3_data = 'd0;
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// internal signals
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wire [24:0] p1_data_1_p_s;
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wire [24:0] p1_data_1_n_s;
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wire [24:0] p1_data_1_s;
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wire [24:0] p1_data_2_p_s;
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wire [24:0] p1_data_2_n_s;
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wire [24:0] p1_data_2_s;
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wire [24:0] p1_data_3_p_s;
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wire [24:0] p1_data_3_n_s;
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wire [24:0] p1_data_3_s;
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wire [24:0] p1_data_4_p_s;
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wire [24:0] p1_data_4_n_s;
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wire [24:0] p1_data_4_s;
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// pipe line stage 1, get the two's complement versions
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assign p1_data_1_p_s = {1'b0, data_1[23:0]};
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assign p1_data_1_n_s = ~p1_data_1_p_s + 1'b1;
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assign p1_data_1_s = (data_1[24] == 1'b1) ? p1_data_1_n_s : p1_data_1_p_s;
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assign p1_data_2_p_s = {1'b0, data_2[23:0]};
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assign p1_data_2_n_s = ~p1_data_2_p_s + 1'b1;
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assign p1_data_2_s = (data_2[24] == 1'b1) ? p1_data_2_n_s : p1_data_2_p_s;
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assign p1_data_3_p_s = {1'b0, data_3[23:0]};
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assign p1_data_3_n_s = ~p1_data_3_p_s + 1'b1;
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assign p1_data_3_s = (data_3[24] == 1'b1) ? p1_data_3_n_s : p1_data_3_p_s;
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assign p1_data_4_p_s = {1'b0, data_4[23:0]};
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assign p1_data_4_n_s = ~p1_data_4_p_s + 1'b1;
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assign p1_data_4_s = (data_4[24] == 1'b1) ? p1_data_4_n_s : p1_data_4_p_s;
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always @(posedge clk) begin
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p1_ddata <= ddata_in;
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p1_data_1 <= p1_data_1_s;
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p1_data_2 <= p1_data_2_s;
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p1_data_3 <= p1_data_3_s;
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p1_data_4 <= p1_data_4_s;
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end
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// pipe line stage 2, get the sum (intermediate, 4->2)
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always @(posedge clk) begin
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p2_ddata <= p1_ddata;
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p2_data_0 <= p1_data_1 + p1_data_2;
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p2_data_1 <= p1_data_3 + p1_data_4;
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end
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// pipe line stage 3, get the sum (final, 2->1)
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always @(posedge clk) begin
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p3_ddata <= p2_ddata;
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p3_data <= p2_data_0 + p2_data_1;
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end
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// output registers, output is unsigned (0 if sum is < 0) and saturated.
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// the inputs are expected to be 1.4.20 format (output is 8bits).
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always @(posedge clk) begin
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ddata_out <= p3_ddata;
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if (p3_data[24] == 1'b1) begin
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data_p <= 8'h00;
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end else if (p3_data[23:20] == 'd0) begin
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data_p <= p3_data[19:12];
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end else begin
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data_p <= 8'hff;
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end
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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