51 lines
1.7 KiB
Verilog
51 lines
1.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_rst (
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// clock reset
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input preset,
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input clk,
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output reg rst);
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// internal registers
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reg ad_rst_sync_m1 = 'd0 /* synthesis preserve */;
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reg ad_rst_sync = 'd0 /* synthesis preserve */;
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// simple reset gen
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always @(posedge clk) begin
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ad_rst_sync_m1 <= preset;
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ad_rst_sync <= ad_rst_sync_m1;
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rst <= ad_rst_sync;
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end
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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