5f307f862f
The axi_dmac core generates requests which are both AXI3 and AXI4 compliant. This means it is possible to connect it to both a AXI3 or AXI4 slave port without needing a AXI protocol converter. Unfortunately it is not possible to declare a port as both AXI3 and AXI4 compliant, so the core has the C_DMA_AXI_PROTCOL_SRC and C_DMA_AXI_PROTOCOL_DEST parameters, which allow to configure the protocol type of the corresponding AXI master interface. Currently the default is always AXI4. But when being used on ZYNQ it is most likely that the AXI master interface of the DMAC core ends up being connected to the AXI3, so change the default to AXI3 if the core is instantiated in a ZYNQ design. The default can still be overwritten by explicitly setting the configuration property. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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bd.tcl |