139876d28a
Currently the clock monitor features a hold register in the monitored clock domain. This old register is used to store a instantaneous copy of the counter register. The value in the old register is then transferred to the monitoring domain. Since the counter is continuously counting it is not possible to directly transfer it since that might result in inconsistent data. Instead stop the counter and hold the registers stable for a duration that is long enough for the monitoring domain to correctly capture the value. Once the value has been transferred the counter is reset and restarted for the next iteration. This allows to eliminate the hold register, which slightly reduces utilization. The externally visible behaviour is identical before and after the patch. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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