98 lines
3.8 KiB
Verilog
98 lines
3.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// serial data output interface: serdes(x8)
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`timescale 1ps/1ps
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module ad_serdes_out #(
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// parameters
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parameter DEVICE_TYPE = 0,
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parameter DATA_WIDTH = 16) (
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// reset and clocks
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input rst,
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input clk,
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input div_clk,
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input loaden,
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// data interface
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input [(DATA_WIDTH-1):0] data_s0,
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input [(DATA_WIDTH-1):0] data_s1,
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input [(DATA_WIDTH-1):0] data_s2,
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input [(DATA_WIDTH-1):0] data_s3,
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input [(DATA_WIDTH-1):0] data_s4,
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input [(DATA_WIDTH-1):0] data_s5,
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input [(DATA_WIDTH-1):0] data_s6,
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input [(DATA_WIDTH-1):0] data_s7,
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output [(DATA_WIDTH-1):0] data_out_p,
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output [(DATA_WIDTH-1):0] data_out_n);
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// defaults
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assign data_out_n = 'd0;
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// instantiations
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genvar l_inst;
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generate
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for (l_inst = 0; l_inst < DATA_WIDTH; l_inst = l_inst + 1) begin: g_data
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alt_serdes_out_core i_core (
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.clk_export (clk),
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.div_clk_export (div_clk),
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.loaden_export (loaden),
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.data_out_export (data_out_p[l_inst]),
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.data_s_export ({ data_s0[l_inst],
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data_s1[l_inst],
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data_s2[l_inst],
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data_s3[l_inst],
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data_s4[l_inst],
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data_s5[l_inst],
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data_s6[l_inst],
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data_s7[l_inst]}));
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end
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endgenerate
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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