c6c45fe1d5
In phase aligned mode the fPLL uses an external feedback path to better align the phase of the PLL output to the phase of the external reference clock. This mode is required for deterministic latency to be able to sample SYSREF which is source synchronous to the external reference clock signal. So far phase aligned mode had been disabled since manual PLL calibration would fail in this mode under certain (unknown) circumstances and dynamic reconfiguration of the PLL would not work. The latest Intel Arria 10 transceiver datasheet contains instructions for the proper calibration sequence to make it work when the PLL is configured for phase aligned mode. Software has been updated accordingly, so enable phase aligned mode. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
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| .. | ||
| adi_jesd204 | ||
| avl_adxcfg | ||
| avl_adxcvr | ||
| avl_adxcvr_octet_swap | ||
| avl_adxphy | ||
| avl_dacfifo | ||
| axi_adxcvr | ||
| common | ||
| jesd204_phy | ||
| util_clkdiv | ||