151 lines
3.8 KiB
Verilog
151 lines
3.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1 ns / 1 ns
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module cic_decim (
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input clk,
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input clk_enable,
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input [4:0] filter_enable,
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input reset,
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input [11:0] filter_in,
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input [2:0] rate_sel,
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output [11:0] filter_out,
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output ce_out
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);
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localparam NUM_STAGES = 6;
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localparam DATA_WIDTH = 106;
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reg [11:0] filter_input_stage = 'h00;
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wire signed [DATA_WIDTH-1:0] data_stage[0:NUM_STAGES*2];
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wire signed [DATA_WIDTH-1:0] data_final_stage;
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reg [16:0] counter = 'h00;
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reg ce_comb = 1'b0;
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reg ce_out_reg = 1'b0;
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reg [11:0] data_out = 'h00;
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reg [15:0] rate;
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wire [4:0] enable = (clk_enable == 1'b1) ? filter_enable : 5'b0;
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always @(*) begin
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case (rate_sel)
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3'h1: rate <= 16'd5 - 1;
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3'h2: rate <= 16'd50 - 1;
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3'h3: rate <= 16'd500 - 1;
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3'h6: rate <= 16'd5000 - 1;
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default: rate <= 16'd50000 - 1;
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endcase
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end
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wire [15:0] counter_in = counter[16] == 1'b1 ? rate : counter[15:0];
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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counter <= {1'b1,16'h00};
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end else if (clk_enable == 1'b1 && enable[0] == 1'b1) begin
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counter <= counter_in - 1'b1;
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end
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end
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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ce_comb <= 1'b0;
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end else begin
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ce_comb <= enable[0] & counter[16];
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end
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end
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always @(posedge clk) begin
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if (enable[0] == 1'b1) begin
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filter_input_stage <= filter_in;
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end
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end
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assign data_stage[0] = $signed(filter_input_stage);
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generate
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genvar i;
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for (i = 0; i < NUM_STAGES; i = i + 1) begin
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cic_int #(
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.DATA_WIDTH(DATA_WIDTH),
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.NUM_STAGES(5),
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.STAGE_WIDTH(20)
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) i_int (
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.clk(clk),
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.ce(enable),
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.data_in(data_stage[i]),
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.data_out(data_stage[i+1])
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);
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end
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endgenerate
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cic_comb #(
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.DATA_WIDTH(DATA_WIDTH),
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.SEQ(5),
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.NUM_STAGES(5),
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.STAGE_WIDTH(20)
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) i_comb0 (
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.clk(clk),
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.ce(ce_comb),
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.enable(filter_enable),
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.data_in(data_stage[6]),
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.data_out(data_stage[11])
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);
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cic_comb #(
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.DATA_WIDTH(DATA_WIDTH),
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.SEQ(1),
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.NUM_STAGES(5),
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.STAGE_WIDTH(20)
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) i_comb1 (
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.clk(clk),
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.ce(ce_comb),
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.enable(filter_enable),
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.data_in(data_stage[11]),
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.data_out(data_stage[12])
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);
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assign data_final_stage = data_stage[2*NUM_STAGES];
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always @(posedge clk) begin
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if (ce_comb == 1'b1) begin
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case (rate_sel)
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'h1: data_out <= data_final_stage[25:14];
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'h2: data_out <= data_final_stage[45:34];
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'h3: data_out <= data_final_stage[65:54];
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'h6: data_out <= data_final_stage[85:74];
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default: data_out <= data_final_stage[105:94];
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endcase
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end
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ce_out_reg <= ce_comb;
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end
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assign ce_out = ce_out_reg;
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assign filter_out = data_out;
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endmodule // cic_decim
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