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pluto_hdl_adi/projects/common
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stefan.raus 9d5de2fc21 Update Vivado version to 2020.2 
Update vivado version to 2020.2:
 - update default vivado version from 2020.1 to 2020.2
 - add conditions to apply specific contraints only in Out Of Context mode.
 - update DDR controler parameters for vcu118 and kcu105 dev boards
 		2021-07-29 14:06:42 +03:00
..
a10gx sysid_intel: Added sysid to intel projects 2020-09-11 15:46:06 +03:00
a10soc common/a10soc: Bridge support 2021-02-05 10:24:59 +02:00
ac701 system_id: deployed ip 2019-08-06 16:53:11 +03:00
c5soc sysid_intel: Added sysid to intel projects 2020-09-11 15:46:06 +03:00
coraz7s cn0540: Initial commit 2020-05-28 18:49:35 +03:00
de10nano de10nano: Add hps_conv_usb_n signal to stabilize UART lines 2021-01-13 15:36:45 +02:00
intel Update Quartus Prime version from 19.3.0 to 20.1.0 2021-03-08 11:29:33 +02:00
kc705 system_id: deployed ip 2019-08-06 16:53:11 +03:00
kcu105 Update Vivado version to 2020.2 2021-07-29 14:06:42 +03:00
microzed system_id: deployed ip 2019-08-06 16:53:11 +03:00
s10soc common/s10soc: Input ports do not have a current strength property 2020-09-25 12:56:14 +03:00
vc707 vc707: Fix mdio intf 2021-01-15 13:50:53 +02:00
vcu118 Update Vivado version to 2020.2 2021-07-29 14:06:42 +03:00
xilinx adi_fir_filter_bd.tcl: Synchronize the control GPIO input to the core clock 2019-12-03 17:27:56 +02:00
zc702 zynq:all: fix SPI clock constraint 2019-08-09 16:39:56 +03:00
zc706 zynq:all: fix SPI clock constraint 2019-08-09 16:39:56 +03:00
zcu102 zynq:all: fix SPI clock constraint 2019-08-09 16:39:56 +03:00
zed zynq:all: fix SPI clock constraint 2019-08-09 16:39:56 +03:00