222 lines
6.6 KiB
Verilog
222 lines
6.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input [12:0] gpio_bd_i,
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output [ 7:0] gpio_bd_o,
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input rx_ref_clk_p,
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input rx_ref_clk_n,
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input rx_sysref_p,
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input rx_sysref_n,
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output rx_sync_p,
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output rx_sync_n,
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input [ 3:0] rx_data_p,
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input [ 3:0] rx_data_n,
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input tx_ref_clk_p,
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input tx_ref_clk_n,
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input tx_sysref_p,
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input tx_sysref_n,
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input tx_sync_p,
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input tx_sync_n,
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output [ 3:0] tx_data_p,
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output [ 3:0] tx_data_n,
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input trig_p,
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input trig_n,
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input adc_fdb,
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input adc_fda,
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input dac_irq,
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input [ 1:0] clkd_status,
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output adc_pd,
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output dac_txen,
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output dac_reset,
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output clkd_sync,
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output spi_csn_clk,
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output spi_csn_dac,
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output spi_csn_adc,
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output spi_clk,
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inout spi_sdio,
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output spi_dir);
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// internal signals
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wire [94:0] gpio_i;
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wire [94:0] gpio_o;
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wire [ 2:0] spi_csn;
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wire spi_mosi;
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wire spi_miso;
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wire trig;
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wire rx_ref_clk;
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wire rx_sysref;
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wire rx_sync;
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wire tx_ref_clk;
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wire tx_sysref;
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wire tx_sync;
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// spi
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assign spi_csn_adc = spi_csn[2];
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assign spi_csn_dac = spi_csn[1];
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assign spi_csn_clk = spi_csn[0];
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// instantiations
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IBUFDS_GTE4 i_ibufds_rx_ref_clk (
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.CEB (1'd0),
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.I (rx_ref_clk_p),
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.IB (rx_ref_clk_n),
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.O (rx_ref_clk),
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.ODIV2 ());
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IBUFDS i_ibufds_rx_sysref (
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.I (rx_sysref_p),
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.IB (rx_sysref_n),
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.O (rx_sysref));
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OBUFDS i_obufds_rx_sync (
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.I (rx_sync),
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.O (rx_sync_p),
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.OB (rx_sync_n));
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IBUFDS_GTE4 i_ibufds_tx_ref_clk (
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.CEB (1'd0),
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.I (tx_ref_clk_p),
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.IB (tx_ref_clk_n),
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.O (tx_ref_clk),
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.ODIV2 ());
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IBUFDS i_ibufds_tx_sysref (
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.I (tx_sysref_p),
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.IB (tx_sysref_n),
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.O (tx_sysref));
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IBUFDS i_ibufds_tx_sync (
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.I (tx_sync_p),
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.IB (tx_sync_n),
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.O (tx_sync));
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daq2_spi i_spi (
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.spi_csn (spi_csn),
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.spi_clk (spi_clk),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_miso),
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.spi_sdio (spi_sdio),
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.spi_dir (spi_dir));
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IBUFDS i_ibufds_trig (
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.I (trig_p),
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.IB (trig_n),
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.O (trig));
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assign adc_pd = gpio_o[42];
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assign dac_txen = gpio_o[41];
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assign dac_reset = gpio_o[40];
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assign clkd_sync = gpio_o[38];
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assign gpio_bd_o = gpio_o[7:0];
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assign gpio_i[94:44] = gpio_o[94:44];
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assign gpio_i[43:43] = trig;
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assign gpio_i[42:37] = gpio_o[42:37];
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assign gpio_i[36:36] = adc_fdb;
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assign gpio_i[35:35] = adc_fda;
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assign gpio_i[34:34] = dac_irq;
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assign gpio_i[33:32] = clkd_status;
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assign gpio_i[31:21] = gpio_o[31:21];
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assign gpio_i[20: 8] = gpio_bd_i;
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assign gpio_i[ 7: 0] = gpio_o[7:0];
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system_wrapper i_system_wrapper (
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.ps_intr_00 (1'd0),
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.ps_intr_01 (1'd0),
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.ps_intr_02 (1'd0),
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.ps_intr_03 (1'd0),
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.ps_intr_04 (1'd0),
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.ps_intr_05 (1'd0),
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.ps_intr_06 (1'd0),
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.ps_intr_07 (1'd0),
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.ps_intr_08 (1'd0),
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.ps_intr_09 (1'd0),
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.ps_intr_10 (1'd0),
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.ps_intr_11 (1'd0),
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.ps_intr_14 (1'd0),
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.ps_intr_15 (1'd0),
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.rx_data_0_n (rx_data_n[0]),
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.rx_data_0_p (rx_data_p[0]),
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.rx_data_1_n (rx_data_n[1]),
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.rx_data_1_p (rx_data_p[1]),
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.rx_data_2_n (rx_data_n[2]),
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.rx_data_2_p (rx_data_p[2]),
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.rx_data_3_n (rx_data_n[3]),
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.rx_data_3_p (rx_data_p[3]),
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.rx_ref_clk_0 (rx_ref_clk),
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.rx_sync_0 (rx_sync),
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.rx_sysref_0 (rx_sysref),
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.spi0_csn (spi_csn),
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.spi0_miso (spi_miso),
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.spi0_mosi (spi_mosi),
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.spi0_sclk (spi_clk),
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.spi1_csn (),
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.spi1_miso (1'd0),
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.spi1_mosi (),
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.spi1_sclk (),
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.tx_data_0_n (tx_data_n[0]),
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.tx_data_0_p (tx_data_p[0]),
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.tx_data_1_n (tx_data_n[1]),
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.tx_data_1_p (tx_data_p[1]),
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.tx_data_2_n (tx_data_n[2]),
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.tx_data_2_p (tx_data_p[2]),
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.tx_data_3_n (tx_data_n[3]),
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.tx_data_3_p (tx_data_p[3]),
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.tx_ref_clk_0 (tx_ref_clk),
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.tx_sync_0 (tx_sync),
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.tx_sysref_0 (tx_sysref));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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