576 lines
15 KiB
Plaintext
576 lines
15 KiB
Plaintext
TITLE
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Transceiver TDD Control (axi_ad*)
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TDD_CNTRL
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ENDTITLE
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############################################################################################
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############################################################################################
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REG
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0x0010
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REG_TDD_CONTROL_0
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TDD Control & Status
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ENDREG
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FIELD
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[5] 0x0
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TDD_GATED_TX_DMAPATH
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RW
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If this bit is set, the core requests data from the TX DMA, just when the data path is active.
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Otherwise will requests continuously on the adjusted rate. The purpose of this feature is to
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facilitate debug. This bit must be SET to preserve data integrity.
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ENDFIELD
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FIELD
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[4] 0x0
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TDD_GATED_RX_DMAPATH
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RW
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If this bit is set, the core provides data for the RX DMA, just when the data path is active.
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Otherwise will provides continuously on the adjusted rate. The purpose of this feature is to
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facilitate debug. This bit must be SET to preserve data integrity.
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ENDFIELD
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FIELD
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[3] 0x0
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TDD_TXONLY
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RW
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If this bit is set- the TDD controller ignores all the TX_* timing registers
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below and assumes continuous receive operation within a frame.
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ENDFIELD
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FIELD
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[2] 0x0
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TDD_RXONLY
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RW
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If this bit is set- the TDD controller ignores all the RX_* timing registers
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below and assumes continuous transmit operation within a frame.
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ENDFIELD
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FIELD
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[1] 0x0
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TDD_SECONDARY
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RW
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Enable the secondary transmit/receive on the active frame. If this bit is clear -
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the controller only uses the _1 timing registers below. If this bit is set -
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the controller uses the _1 and _2 timing registers below.
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ENDFIELD
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FIELD
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[0] 0x0
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TDD_ENABLE
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RW
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If set, enables the TDD controller- software must set this bit after programming
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all the registers that controls the tdd timing. Any device settings needs to be
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done (for example bring the AD9361 to the alert state) prior to to setting this
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bit. The controller keeps the frame counters in reset if this bit is reset.
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A 0 to 1 transition in this bit starts the frame counter and tdd mode of operation.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0011
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REG_TDD_CONTROL_1
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TDD Control & Status
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ENDREG
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FIELD
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[7:0] 0x00
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TDD_BURST_COUNT
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RW
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If set to 0x0 and enabled (TDD_ENABLE is set) - the controller operates in TDD mode
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as long as the TDD_ENABLE bit is set. If set to a non-zero value, the controller
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operates for the set number of frames and stops.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0012
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REG_TDD_CONTROL_2
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_COUNTER_INIT
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RW
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The controller sets the frame counter to this value when starting TDD operation.
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This is the starting offset value for the TDD frame counter.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0013
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REG_TDD_FRAME_LENGTH
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_FRAME_LENGTH
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RW
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The frame length is the terminal count for the 10ms counter running at the digital
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interface clock- as an example for a 245.76MHz clock it is 0x258000.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0014
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REG_TDD_SYNC_TERMINAL_TYPE
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TDD Control & Status
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ENDREG
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FIELD
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[0] 0x0
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TDD_SYNC_TERMINAL_TYPE
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RW
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Set this bit, if the current terminal will generate the syncronization pulse, reset otherwise.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0018
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REG_TDD_STATUS
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TDD Control & Status
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ENDREG
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FIELD
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[0] 0x0
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TDD_RXTX_VCO_OVERLAP
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RO
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This bit is asserted, if exist a time interval when both the TX and RX VCOs are powered up.
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ENDFIELD
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FIELD
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[1] 0x0
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TDD_RXTX_RF_OVERLAP
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RO
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This bit is asserted, if exist a time interval when both the TX and RX RF datapath are powered up.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0020
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REG_TDD_VCO_RX_ON_1
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_VCO_RX_ON_1
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RW
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Defines the offset (from frame count equal zero), when the RX VCO powers up at the first time.
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The controller enables the receive VCO, when the frame count reaches this value.
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The VCO may have to be enabled before data can be received. The user needs to make sure,
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that the RF device is in a state, from where this operation is valid.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0021
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REG_TDD_VCO_RX_OFF_1
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_VCO_RX_OFF_1
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RW
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Defines the offset (from frame count equal zero), when the RX VCO powers down at the first
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time. The controller disables the receive VCO, when the frame count reaches this value.
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The user needs to make sure, that the RF device is in a state, from where this operation
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is valid.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0022
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REG_TDD_VCO_TX_ON_1
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_VCO_TX_ON_1
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RW
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Defines the offset (from frame count equal zero), when the TX VCO powers up at the first time.
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The controller enables the transmit VCO, when the frame count reaches this value. The user
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needs to make sure, that the RF device is in a state, from where this operation is valid.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0023
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REG_TDD_VCO_TX_OFF_1
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_VCO_TX_OFF_1
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RW
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Defines the offset (from frame count equal zero), when the TX VCO powers down at the first
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time. The controller disables the transmit VCO when the frame count reaches this value.
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The user needs to make sure, that the RF device is in a state, from where this operation
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is valid.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0024
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REG_TDD_RX_ON_1
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_RX_ON_1
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RW
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Defines the offset (from frame count equal zero), when the RX data path is activated at the
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first time. The controller enables the receive chain when the frame count reaches this value.
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The user needs to make sure, that the RF device is in a state, from where this operation is valid.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0025
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REG_TDD_RX_OFF_1
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_RX_OFF_1
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RW
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Defines the offset (from frame count equal zero), when the RX data path is deactivated the
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first time. The controller disables the receive chain when the frame
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count reaches this value. The user needs to make sure, that the RF device is in
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a state, from where this operation is valid.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0026
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REG_TDD_TX_ON_1
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_TX_ON_1
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RW
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Defines the offset (from frame count equal zero), when the TX data path is activated at the
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first time. The controller enables the transmit chain, when the frame
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count reaches this value. This register and the TX_DP_ON register controls
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the delay between the data path being activated and the time to actually push the
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transmit data through the transmit chain in the device.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0027
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REG_TDD_TX_OFF_1
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_TX_OFF_1
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RW
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Defines the offset (from frame count equal zero), when the TX data path is deactivated at the
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first time. The controller disables the transmit chain, when the frame
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count reaches this value. This register and the TX_DP_OFF register controls the
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delay between the data path being deactivated and the time to actually stop
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transmitting data through the transmit chain in the device.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0028
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REG_TDD_RX_DP_ON_1
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_RX_DP_ON_1
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RW
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Defines the offset (from frame count equal zero), when the controller starts to accept data from
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the digital interface for receive.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0029
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REG_TDD_RX_DP_OFF_1
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_RX_DP_OFF_1
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RW
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Defines the offset (from frame count equal zero), when the controller stops to accept data from
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the digital interface for receive.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x002A
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REG_TDD_TX_DP_ON_1
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_TX_DP_ON_1
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RW
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Defines the offset (from frame count equal zero), when the controller starts to request data from the system
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memory for transmit. The data rate is controlled by the TDD controller.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x002B
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REG_TDD_TX_DP_OFF_1
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_TX_DP_OFF_1
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RW
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Defines the offset (from frame count equal zero), when the controller stop requesting data from the system
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memory for transmit.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0030
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REG_TDD_VCO_RX_ON_2
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_VCO_RX_ON_2
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RW
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The secondary pointer for VCO_RX_ON.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0031
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REG_TDD_VCO_RX_OFF_2
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_VCO_RX_OFF_2
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RW
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The secondary pointer for VCO_RX_OFF.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0032
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REG_TDD_VCO_TX_ON_2
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_VCO_TX_ON_2
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RW
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The secondary pointer for VCO_TX_ON.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0033
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REG_TDD_VCO_TX_OFF_2
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_VCO_TX_OFF_2
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RW
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The secondary pointer for VCO_TX_OFF.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0034
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REG_TDD_RX_ON_2
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_RX_ON_2
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RW
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The secondary pointer for RX_ON.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0035
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REG_TDD_RX_OFF_2
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_RX_OFF_2
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RW
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The secondary pointer for RX_OFF.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0036
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REG_TDD_TX_ON_2
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_TX_ON_2
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RW
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The secondary pointer for TX_ON.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0037
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REG_TDD_TX_OFF_2
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_TX_OFF_2
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RW
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The secondary pointer for TX_OFF.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0038
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REG_TDD_RX_DP_ON_2
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_RX_DP_ON_2
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RW
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The secondary pointer for RX_DP_ON.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x0039
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REG_TDD_RX_DP_OFF_2
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_RX_DP_OFF_2
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RW
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The secondary pointer for RX_DP_OFF.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x003A
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REG_TDD_TX_DP_ON_2
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_TX_DP_ON_2
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RW
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The secondary pointer for TX_DP_ON.
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ENDFIELD
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############################################################################################
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############################################################################################
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REG
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0x003B
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REG_TDD_TX_DP_OFF_2
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TDD Control & Status
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ENDREG
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FIELD
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[23:0] 0x000000
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TDD_TX_DP_OFF_2
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RW
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The secondary pointer for TX_DP_OFF.
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ENDFIELD
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############################################################################################
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############################################################################################
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