98 lines
2.4 KiB
Verilog
98 lines
2.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2017, 2018, 2021, 2022 Analog Devices, Inc. All rights reserved.
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// SPDX short identifier: ADIJESD204
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module sync_header_align (
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input clk,
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input reset,
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input [65:0] i_data,
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output i_slip,
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input i_slip_done,
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output [63:0] o_data,
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output [1:0] o_header,
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output o_block_sync
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);
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assign {o_header,o_data} = i_data;
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// TODO : Add alignment FSM
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localparam STATE_SH_HUNT = 3'b001;
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localparam STATE_SH_SLIP = 3'b010;
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localparam STATE_SH_LOCK = 3'b100;
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localparam BIT_SH_HUNT = 0;
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localparam BIT_SH_SLIP = 1;
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localparam BIT_SH_LOCK = 2;
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localparam RX_THRESH_SH_ERR = 16;
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localparam LOG2_RX_THRESH_SH_ERR = $clog2(RX_THRESH_SH_ERR);
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reg [2:0] state = STATE_SH_HUNT;
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reg [2:0] next_state;
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reg [7:0] header_vcnt = 8'h0;
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reg [LOG2_RX_THRESH_SH_ERR:0] header_icnt = 'h0;
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wire valid_header;
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assign valid_header = ^o_header;
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always @(posedge clk) begin
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if (reset | ~valid_header) begin
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header_vcnt <= 'b0;
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end else if (state[BIT_SH_HUNT] & ~header_vcnt[7]) begin
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header_vcnt <= header_vcnt + 'b1;
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end
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end
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always @(posedge clk) begin
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if (reset | valid_header) begin
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header_icnt <= 'b0;
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end else if (state[BIT_SH_LOCK] & ~header_icnt[LOG2_RX_THRESH_SH_ERR]) begin
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header_icnt <= header_icnt + 'b1;
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end
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end
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always @(*) begin
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next_state = state;
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case (state)
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STATE_SH_HUNT:
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if (valid_header) begin
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if (header_vcnt[7]) begin
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next_state = STATE_SH_LOCK;
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end
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end else begin
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next_state = STATE_SH_SLIP;
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end
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STATE_SH_SLIP:
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if (i_slip_done) begin
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next_state = STATE_SH_HUNT;
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end
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STATE_SH_LOCK:
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if (~valid_header) begin
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if (header_icnt[LOG2_RX_THRESH_SH_ERR]) begin
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next_state = STATE_SH_HUNT;
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end
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end
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endcase
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end
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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state <= STATE_SH_HUNT;
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end else begin
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state <= next_state;
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end
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end
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assign o_block_sync = state[BIT_SH_LOCK];
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assign i_slip = state[BIT_SH_SLIP];
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endmodule
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