235 lines
6.8 KiB
Verilog
235 lines
6.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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input [12:0] gpio_bd_i,
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output [ 7:0] gpio_bd_o,
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input rx_ref_clk_p,
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input rx_ref_clk_n,
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input rx_device_clk_p,
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input rx_device_clk_n,
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output rx_sync0_p,
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output rx_sync0_n,
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output rx_sync1_p,
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output rx_sync1_n,
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input rx_sysref_p,
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input rx_sysref_n,
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input [ 3:0] rx_data_p,
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input [ 3:0] rx_data_n,
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inout adc_fdb,
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inout adc_fda,
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inout adc_pdwn,
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// DAQ board's ADC SPI
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output spi_adc_csn,
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output spi_adc_clk,
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output spi_adc_mosi,
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input spi_adc_miso,
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// DAQ board's clock chip
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output spi_clkgen_csn,
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output spi_clkgen_clk,
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output spi_clkgen_mosi,
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input spi_clkgen_miso,
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// DAQ board's vco chip
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output spi_vco_csn,
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output spi_vco_clk,
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output spi_vco_mosi,
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// AFE board's DAC
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inout afe_dac_sda,
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inout afe_dac_scl,
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output afe_dac_clr_n,
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output afe_dac_load,
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// AFE board's ADC
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output afe_adc_sclk,
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output afe_adc_scn,
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input afe_adc_sdi,
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output afe_adc_convst,
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// Laser driver differential line
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output laser_driver_p,
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output laser_driver_n,
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output laser_driver_en_n,
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input laser_driver_otw_n,
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// GPIO's for the laser board
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inout [13:0] laser_gpio,
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// Vref selects for AFE board
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output [ 7:0] tia_chsel
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);
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// internal signals
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wire [94:0] gpio_i;
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wire [94:0] gpio_o;
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wire [94:0] gpio_t;
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wire rx_ref_clk;
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wire rx_sync;
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wire rx_sysref;
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wire rx_device_clk;
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wire rx_device_clk_ds;
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wire laser_driver;
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// instantiations
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IBUFDS_GTE4 i_ibufds_rx_ref_clk (
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.CEB (1'd0),
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.I (rx_ref_clk_p),
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.IB (rx_ref_clk_n),
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.O (rx_ref_clk),
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.ODIV2 ());
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OBUFDS i_obufds_rx_sync0 (
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.I (rx_sync),
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.O (rx_sync0_p),
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.OB (rx_sync0_n));
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OBUFDS i_obufds_rx_sync1 (
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.I (rx_sync),
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.O (rx_sync1_p),
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.OB (rx_sync1_n));
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IBUFDS i_rx_device_clk_ds (
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.I (rx_device_clk_p),
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.IB (rx_device_clk_n),
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.O (rx_device_clk_ds));
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BUFG i_rx_device_clk (
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.I (rx_device_clk_ds),
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.O (rx_device_clk));
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IBUFDS i_rx_sysref (
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.I (rx_sysref_p),
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.IB (rx_sysref_n),
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.O (rx_sysref));
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// laser driver
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OBUFDS i_obufds_laser_driver (
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.I (laser_driver),
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.O (laser_driver_p),
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.OB (laser_driver_n));
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// GPIO connections to the FMC connector
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ad_iobuf #(
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.DATA_WIDTH(20)
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) i_fmc_iobuf (
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.dio_t ({gpio_t[51:38], 3'b0, gpio_t[34:32]}),
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.dio_i ({gpio_o[51:32]}),
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.dio_o ({gpio_i[51:32]}),
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.dio_p ({
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laser_gpio, // 51:38
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afe_adc_convst, // 37 - output only
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afe_dac_load, // 36 - output only
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afe_dac_clr_n, // 35 - output only
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adc_pdwn, // 34
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adc_fdb, // 33
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adc_fda // 32
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}));
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assign gpio_bd_o = gpio_o[ 7: 0];
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assign gpio_i[20: 8] = gpio_bd_i;
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assign gpio_i[ 7: 0] = gpio_o[ 7: 0];
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assign gpio_i[31:21] = gpio_o[31:21];
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assign gpio_i[94:52] = gpio_o[94:52];
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// block design instance
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system_wrapper i_system_wrapper (
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.rx_data_0_n (rx_data_n[0]),
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.rx_data_0_p (rx_data_p[0]),
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.rx_data_1_n (rx_data_n[1]),
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.rx_data_1_p (rx_data_p[1]),
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.rx_data_2_n (rx_data_n[2]),
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.rx_data_2_p (rx_data_p[2]),
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.rx_data_3_n (rx_data_n[3]),
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.rx_data_3_p (rx_data_p[3]),
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.rx_ref_clk (rx_ref_clk),
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.rx_device_clk (rx_device_clk),
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.rx_sync_0 (rx_sync),
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.rx_sysref_0 (rx_sysref),
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.laser_driver (laser_driver),
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.laser_driver_en_n (laser_driver_en_n),
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.laser_driver_otw_n (laser_driver_otw_n),
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.tia_chsel (tia_chsel),
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.iic_dac_scl_io (afe_dac_scl),
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.iic_dac_sda_io (afe_dac_sda),
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.spi0_sclk (spi_adc_clk),
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.spi0_csn (spi_adc_csn),
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.spi0_miso (spi_adc_miso),
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.spi0_mosi (spi_adc_mosi),
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.spi1_sclk (spi_clkgen_clk),
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.spi1_csn (spi_clkgen_csn),
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.spi1_miso (spi_clkgen_miso),
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.spi1_mosi (spi_clkgen_mosi),
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.spi_vco_csn_i (1'b1),
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.spi_vco_csn_o (spi_vco_csn),
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.spi_vco_clk_i (1'b0),
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.spi_vco_clk_o (spi_vco_clk),
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.spi_vco_sdo_i (1'b0),
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.spi_vco_sdo_o (spi_vco_mosi),
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.spi_vco_sdi_i (1'b0),
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.spi_afe_adc_csn_i (1'b1),
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.spi_afe_adc_csn_o (afe_adc_scn),
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.spi_afe_adc_clk_i (1'b0),
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.spi_afe_adc_clk_o (afe_adc_sclk),
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.spi_afe_adc_sdo_i (1'b0),
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.spi_afe_adc_sdo_o (),
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.spi_afe_adc_sdi_i (afe_adc_sdi));
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endmodule
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