387 lines
11 KiB
Verilog
387 lines
11 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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DDR_addr,
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DDR_ba,
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DDR_cas_n,
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DDR_ck_n,
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DDR_ck_p,
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DDR_cke,
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DDR_cs_n,
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DDR_dm,
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DDR_dq,
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DDR_dqs_n,
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DDR_dqs_p,
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DDR_odt,
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DDR_ras_n,
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DDR_reset_n,
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DDR_we_n,
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FIXED_IO_ddr_vrn,
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FIXED_IO_ddr_vrp,
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FIXED_IO_mio,
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FIXED_IO_ps_clk,
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FIXED_IO_ps_porb,
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FIXED_IO_ps_srstb,
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gpio_bd,
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hdmi_out_clk,
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hdmi_vsync,
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hdmi_hsync,
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hdmi_data_e,
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hdmi_data,
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i2s_mclk,
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i2s_bclk,
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i2s_lrclk,
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i2s_sdata_out,
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i2s_sdata_in,
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spdif,
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dac_clk_in_p,
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dac_clk_in_n,
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dac_clk_out_p,
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dac_clk_out_n,
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dac_frame_out_p,
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dac_frame_out_n,
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dac_data_out_p,
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dac_data_out_n,
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adc_clk_in_p,
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adc_clk_in_n,
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adc_or_in_p,
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adc_or_in_n,
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adc_data_in_p,
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adc_data_in_n,
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ref_clk_out_p,
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ref_clk_out_n,
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iic_scl,
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iic_sda,
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iic_mux_scl,
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iic_mux_sda,
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otg_vbusoc);
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inout [14:0] DDR_addr;
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inout [ 2:0] DDR_ba;
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inout DDR_cas_n;
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inout DDR_ck_n;
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inout DDR_ck_p;
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inout DDR_cke;
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inout DDR_cs_n;
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inout [ 3:0] DDR_dm;
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inout [31:0] DDR_dq;
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inout [ 3:0] DDR_dqs_n;
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inout [ 3:0] DDR_dqs_p;
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inout DDR_odt;
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inout DDR_ras_n;
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inout DDR_reset_n;
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inout DDR_we_n;
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inout FIXED_IO_ddr_vrn;
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inout FIXED_IO_ddr_vrp;
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inout [53:0] FIXED_IO_mio;
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inout FIXED_IO_ps_clk;
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inout FIXED_IO_ps_porb;
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inout FIXED_IO_ps_srstb;
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inout [31:0] gpio_bd;
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output hdmi_out_clk;
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output hdmi_vsync;
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output hdmi_hsync;
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output hdmi_data_e;
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output [15:0] hdmi_data;
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output spdif;
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output i2s_mclk;
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output i2s_bclk;
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output i2s_lrclk;
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output i2s_sdata_out;
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input i2s_sdata_in;
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input dac_clk_in_p;
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input dac_clk_in_n;
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output dac_clk_out_p;
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output dac_clk_out_n;
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output dac_frame_out_p;
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output dac_frame_out_n;
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output [15:0] dac_data_out_p;
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output [15:0] dac_data_out_n;
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input adc_clk_in_p;
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input adc_clk_in_n;
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input adc_or_in_p;
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input adc_or_in_n;
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input [13:0] adc_data_in_p;
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input [13:0] adc_data_in_n;
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output ref_clk_out_p;
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output ref_clk_out_n;
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inout iic_scl;
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inout iic_sda;
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inout [ 1:0] iic_mux_scl;
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inout [ 1:0] iic_mux_sda;
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input otg_vbusoc;
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// internal registers
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reg [63:0] dac_ddata_0 = 'd0;
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reg [63:0] dac_ddata_1 = 'd0;
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reg dac_dma_rd = 'd0;
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reg adc_data_cnt = 'd0;
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reg adc_dma_wr = 'd0;
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reg [31:0] adc_dma_wdata = 'd0;
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// internal signals
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wire [31:0] gpio_i;
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wire [31:0] gpio_o;
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wire [31:0] gpio_t;
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wire dac_clk;
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wire dac_valid_0;
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wire dac_enable_0;
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wire dac_valid_1;
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wire dac_enable_1;
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wire [63:0] dac_dma_rdata;
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wire adc_clk;
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wire adc_valid_0;
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wire adc_enable_0;
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wire [15:0] adc_data_0;
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wire adc_valid_1;
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wire adc_enable_1;
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wire [15:0] adc_data_1;
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wire ref_clk;
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wire oddr_ref_clk;
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wire [ 1:0] iic_mux_scl_i_s;
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wire [ 1:0] iic_mux_scl_o_s;
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wire iic_mux_scl_t_s;
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wire [ 1:0] iic_mux_sda_i_s;
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wire [ 1:0] iic_mux_sda_o_s;
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wire iic_mux_sda_t_s;
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wire [15:0] ps_intrs;
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// instantiations
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ODDR #(
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.DDR_CLK_EDGE ("SAME_EDGE"),
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.INIT (1'b0),
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.SRTYPE ("ASYNC"))
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i_oddr_ref_clk (
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.S (1'b0),
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.CE (1'b1),
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.R (1'b0),
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.C (ref_clk),
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.D1 (1'b1),
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.D2 (1'b0),
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.Q (oddr_ref_clk));
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OBUFDS i_obufds_ref_clk (
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.I (oddr_ref_clk),
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.O (ref_clk_out_p),
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.OB (ref_clk_out_n));
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ad_iobuf #(
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.DATA_WIDTH(32))
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i_gpio_bd (
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.dt(gpio_t),
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.di(gpio_o),
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.do(gpio_i),
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.dio(gpio_bd));
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ad_iobuf #(
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.DATA_WIDTH(2))
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i_iic_mux_scl (
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.dt({iic_mux_scl_t_s, iic_mux_scl_t_s}),
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.di(iic_mux_scl_o_s),
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.do(iic_mux_scl_i_s),
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.dio(iic_mux_scl));
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ad_iobuf #(
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.DATA_WIDTH(2))
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i_iic_mux_sda (
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.dt({iic_mux_sda_t_s, iic_mux_sda_t_s}),
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.di(iic_mux_sda_o_s),
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.do(iic_mux_sda_i_s),
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.dio(iic_mux_sda));
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always @(posedge dac_clk) begin
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dac_dma_rd <= dac_valid_0 & dac_enable_0;
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dac_ddata_1[63:48] <= dac_dma_rdata[63:48];
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dac_ddata_1[47:32] <= dac_dma_rdata[63:48];
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dac_ddata_1[31:16] <= dac_dma_rdata[31:16];
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dac_ddata_1[15: 0] <= dac_dma_rdata[31:16];
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dac_ddata_0[63:48] <= dac_dma_rdata[47:32];
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dac_ddata_0[47:32] <= dac_dma_rdata[47:32];
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dac_ddata_0[31:16] <= dac_dma_rdata[15: 0];
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dac_ddata_0[15: 0] <= dac_dma_rdata[15: 0];
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end
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always @(posedge adc_clk) begin
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adc_data_cnt <= ~adc_data_cnt ;
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case ({adc_enable_1, adc_enable_0})
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2'b10: begin
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adc_dma_wr <= adc_data_cnt;
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adc_dma_wdata <= {adc_data_1, adc_dma_wdata[31:16]};
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end
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2'b01: begin
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adc_dma_wr <= adc_data_cnt;
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adc_dma_wdata <= {adc_data_0, adc_dma_wdata[31:16]};
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end
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default: begin
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adc_dma_wr <= 1'b1;
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adc_dma_wdata <= {adc_data_1, adc_data_0};
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end
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endcase
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end
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system_wrapper i_system_wrapper (
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.DDR_addr (DDR_addr),
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.DDR_ba (DDR_ba),
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.DDR_cas_n (DDR_cas_n),
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.DDR_ck_n (DDR_ck_n),
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.DDR_ck_p (DDR_ck_p),
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.DDR_cke (DDR_cke),
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.DDR_cs_n (DDR_cs_n),
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.DDR_dm (DDR_dm),
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.DDR_dq (DDR_dq),
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.DDR_dqs_n (DDR_dqs_n),
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.DDR_dqs_p (DDR_dqs_p),
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.DDR_odt (DDR_odt),
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.DDR_ras_n (DDR_ras_n),
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.DDR_reset_n (DDR_reset_n),
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.DDR_we_n (DDR_we_n),
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.FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn),
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.FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp),
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.FIXED_IO_mio (FIXED_IO_mio),
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.FIXED_IO_ps_clk (FIXED_IO_ps_clk),
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.FIXED_IO_ps_porb (FIXED_IO_ps_porb),
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.FIXED_IO_ps_srstb (FIXED_IO_ps_srstb),
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.GPIO_I (gpio_i),
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.GPIO_O (gpio_o),
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.GPIO_T (gpio_t),
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.adc_clk (adc_clk),
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.adc_clk_in_n (adc_clk_in_n),
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.adc_clk_in_p (adc_clk_in_p),
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.adc_data_0 (adc_data_0),
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.adc_data_1 (adc_data_1),
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.adc_data_in_n (adc_data_in_n),
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.adc_data_in_p (adc_data_in_p),
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.adc_dma_sync (1'b1),
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.adc_dma_wdata (adc_dma_wdata),
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.adc_dma_wr (adc_dma_wr),
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.adc_enable_0 (adc_enable_0),
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.adc_enable_1 (adc_enable_1),
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.adc_or_in_n (adc_or_in_n),
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.adc_or_in_p (adc_or_in_p),
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.adc_valid_0 (adc_valid_0),
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.adc_valid_1 (adc_valid_1),
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.dac_clk (dac_clk),
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.dac_clk_in_n (dac_clk_in_n),
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.dac_clk_in_p (dac_clk_in_p),
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.dac_clk_out_n (dac_clk_out_n),
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.dac_clk_out_p (dac_clk_out_p),
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.dac_data_out_n (dac_data_out_n),
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.dac_data_out_p (dac_data_out_p),
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.dac_ddata_0 (dac_ddata_0),
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.dac_ddata_1 (dac_ddata_1),
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.dac_dma_rd (dac_dma_rd),
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.dac_dma_rdata (dac_dma_rdata),
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.dac_enable_0 (dac_enable_0),
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.dac_enable_1 (dac_enable_1),
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.dac_frame_out_n (dac_frame_out_n),
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.dac_frame_out_p (dac_frame_out_p),
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.dac_valid_0 (dac_valid_0),
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.dac_valid_1 (dac_valid_1),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.i2s_bclk (i2s_bclk),
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.i2s_lrclk (i2s_lrclk),
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.i2s_mclk (i2s_mclk),
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.i2s_sdata_in (i2s_sdata_in),
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.i2s_sdata_out (i2s_sdata_out),
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.iic_fmc_scl_io (iic_scl),
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.iic_fmc_sda_io (iic_sda),
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.iic_mux_scl_I (iic_mux_scl_i_s),
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.iic_mux_scl_O (iic_mux_scl_o_s),
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.iic_mux_scl_T (iic_mux_scl_t_s),
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.iic_mux_sda_I (iic_mux_sda_i_s),
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.iic_mux_sda_O (iic_mux_sda_o_s),
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.iic_mux_sda_T (iic_mux_sda_t_s),
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.ps_intr_0 (ps_intrs[0]),
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.ps_intr_1 (ps_intrs[1]),
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.ps_intr_10 (ps_intrs[10]),
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.ps_intr_11 (ps_intrs[11]),
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.ps_intr_12 (ps_intrs[12]),
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.ps_intr_13 (ps_intrs[13]),
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.ps_intr_2 (ps_intrs[2]),
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.ps_intr_3 (ps_intrs[3]),
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.ps_intr_4 (ps_intrs[4]),
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.ps_intr_5 (ps_intrs[5]),
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.ps_intr_6 (ps_intrs[6]),
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.ps_intr_7 (ps_intrs[7]),
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.ps_intr_8 (ps_intrs[8]),
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.ps_intr_9 (ps_intrs[9]),
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.ad9122_dma_irq (ps_intrs[12]),
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.ad9643_dma_irq (ps_intrs[13]),
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.iic_fmc_intr(ps_intrs[11]),
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.ref_clk (ref_clk),
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.otg_vbusoc (otg_vbusoc),
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.spdif (spdif));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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