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bd
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axi_dmac: patch version checking
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2018-12-20 10:32:48 +02:00 |
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tb
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library: Add `timescale to modules that are missing it
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2019-05-15 15:37:44 +03:00 |
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2d_transfer.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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Makefile
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Makefile: update makefiles
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2018-12-21 17:32:48 +02:00 |
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address_generator.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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axi_dmac.v
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axi_dmac: Remove length alignment requirement for MM interfaces
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2018-11-30 23:41:49 +02:00 |
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axi_dmac_burst_memory.v
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sync_bits: Change I/O names of wires "in" and "out" for VHDL users
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2019-04-23 18:03:23 +03:00 |
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axi_dmac_constr.sdc
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axi_dmac: preparation work for reporting length of partial transfers
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2018-09-07 11:38:04 +03:00 |
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axi_dmac_constr.ttcl
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axi_dmac: early abort support
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2018-09-07 11:38:04 +03:00 |
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axi_dmac_hw.tcl
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axi_dmac: burst_memory: Add support for using asymmetric memory
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2018-11-30 23:41:49 +02:00 |
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axi_dmac_ip.tcl
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axi_dmac: infer interrupt line for Xilinx projects
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2019-04-25 08:25:02 +03:00 |
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axi_dmac_pkg_sv.ttcl
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axi_dmac: ttcl file support for simulation
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2018-07-11 11:30:22 +03:00 |
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axi_dmac_regmap.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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axi_dmac_regmap_request.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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axi_dmac_reset_manager.v
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sync_bits: Change I/O names of wires "in" and "out" for VHDL users
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2019-04-23 18:03:23 +03:00 |
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axi_dmac_resize_dest.v
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axi_dmac: Remove length alignment requirement for MM interfaces
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2018-11-30 23:41:49 +02:00 |
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axi_dmac_resize_src.v
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axi_dmac: Remove length alignment requirement for MM interfaces
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2018-11-30 23:41:49 +02:00 |
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axi_dmac_response_manager.v
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axi_dmac: burst_memory: Reset beat counter at the end of each burst
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2018-11-30 23:41:49 +02:00 |
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axi_dmac_transfer.v
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axi_dmac: burst_memory: Add support for using asymmetric memory
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2018-11-30 23:41:49 +02:00 |
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axi_register_slice.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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data_mover.v
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Revert "axi_dmac: assert xfer_request only when ready"
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2019-04-18 16:15:55 +03:00 |
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dest_axi_mm.v
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axi_dmac: Remove length alignment requirement for MM interfaces
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2018-11-30 23:41:49 +02:00 |
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dest_axi_stream.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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dest_fifo_inf.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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inc_id.vh
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axi_dmac: renamed .h files to .vh
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2018-07-11 11:30:22 +03:00 |
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request_arb.v
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sync_bits: Change I/O names of wires "in" and "out" for VHDL users
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2019-04-23 18:03:23 +03:00 |
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request_generator.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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resp.vh
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axi_dmac: renamed .h files to .vh
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2018-07-11 11:30:22 +03:00 |
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response_generator.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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response_handler.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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splitter.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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src_axi_mm.v
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axi_dmac: Remove length alignment requirement for MM interfaces
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2018-11-30 23:41:49 +02:00 |
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src_axi_stream.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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src_fifo_inf.v
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Add missing timescale annotations
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2018-10-17 10:32:47 +03:00 |
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