169f38e7d1
The ad_ip_jesd204_tpl_dac currently only supports JESD204 modes that have both N and N' set to 16. Newer DACs like the AD9172 support modes where N and N' are not equal to 16. Add support for these modes. The width of the internal channel data path is set to N, only processing as many bits as necessary. At the framer the data is up-sized to N' bits with tail bits inserted as necessary. This data is then passed to the link layer. The width at the DMA interface is kept at 16 bits per sample regardless of the configuration of either N or N'. This is done to keep the interface consistent with the existing infrastructure it will connect to like upack and DMA. The data is expected to the LSB aligned, the unused MSBs will be ignored. Same is true for the test-pattern data registers. These register keep their existing 16-bit layout, but unused MSBs will be ignored by the core. The PN generators are modified to create only N bits of data per sample. Note that while the core can now support modes with N' = 12 there is still the restriction that requires the number of frames per beat to be an even number. Which means that not all modes with N' = 12 can be supported yet. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
||
|---|---|---|
| library | ||
| projects | ||
| .gitattributes | ||
| .gitignore | ||
| LICENSE | ||
| LICENSE_ADIBSD | ||
| LICENSE_GPL2 | ||
| LICENSE_LGPL | ||
| Makefile | ||
| README.md | ||
| quiet.mk | ||
README.md
HDL Reference Designs
Analog Devices Inc. HDL libraries and projects.
Getting started
This repository supports reference designs for different Analog Devices boards based on Intel and Xilinx FPGA development boards or standalone.
Prerequisites
or
Please make sure that you have the required tool version.
How to build a project
For building a projects, you have to use the GNU Make tool. If you're a Windows user please checkout this page, to see how you can install this tool.
To build a project, checkout the latest release, after that just cd to the project that you want to build and run make:
[~]cd projects/fmcomms2/zc706
[~]make
A more comprehensive build guide can be found under the following link: https://wiki.analog.com/resources/fpga/docs/build
Software
In general all the projects have no-OS (baremetal) and a Linux support. See no-OS or Linux for more information.
Which branch should I use?
-
If you want to use the most stable code base, always use the latest release branch.
-
If you want to use the greatest and latest, check out the master branch.
License
In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.
The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.
See LICENSE for more details. The separate license files cab be found here:
Comprehensive user guide
See HDL User Guide for a more detailed guide.
Support
Feel free to ask any question at EngineerZone.