244 lines
11 KiB
Tcl
244 lines
11 KiB
Tcl
#
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# The ADI JESD204 Core is released under the following license, which is
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# different than all other HDL cores in this repository.
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#
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# Please read this, and understand the freedoms and responsibilities you have
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# by using this source code/core.
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#
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# The JESD204 HDL, is copyright © 2016-2017 Analog Devices Inc.
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#
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# This core is free software, you can use run, copy, study, change, ask
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# questions about and improve this core. Distribution of source, or resulting
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# binaries (including those inside an FPGA or ASIC) require you to release the
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# source of the entire project (excluding the system libraries provide by the
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# tools/compiler/FPGA vendor). These are the terms of the GNU General Public
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# License version 2 as published by the Free Software Foundation.
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#
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# This core is distributed in the hope that it will be useful, but WITHOUT ANY
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# WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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# A PARTICULAR PURPOSE. See the GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License version 2
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# along with this source code, and binary. If not, see
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# <http://www.gnu.org/licenses/>.
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#
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# Commercial licenses (with commercial support) of this JESD204 core are also
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# available under terms different than the General Public License. (e.g. they
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# do not require you to accompany any image (FPGA or ASIC) using the JESD204
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# core with any corresponding source code.) For these alternate terms you must
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# purchase a license from Analog Devices Technology Licensing Office. Users
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# interested in such a license should contact jesd204-licensing@analog.com for
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# more information. This commercial license is sub-licensable (if you purchase
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# chips from Analog Devices, incorporate them into your PCB level product, and
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# purchase a JESD204 license, end users of your product will also have a
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# license to use this core in a commercial setting without releasing their
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# source code).
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#
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# In addition, we kindly ask you to acknowledge ADI in any program, application
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# or publication in which you use this JESD204 HDL core. (You are not required
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# to do so; it is up to your common sense to decide whether you want to comply
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# with this request or not.) For general publications, we suggest referencing :
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# “The design and implementation of the JESD204 HDL Core used in this project
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# is copyright © 2016-2017, Analog Devices, Inc.”
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#
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package require qsys
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip_alt.tcl
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#
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# Instantiates the Arria 10 native PHY and configures it for JESD204 operation.
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# The datapath width is configured for 4 octets per beat.
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#
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# Optionally a soft-logic PCS is instantiated, this can be used if the lane rate
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# is too high for the hard-logic PCS.
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#
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ad_ip_create jesd204_phy "ADI JESD204 PHY"
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set_module_property COMPOSITION_CALLBACK jesd204_phy_composition_callback
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set_module_property INTERNAL true
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# parameters
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ad_ip_parameter ID NATURAL 0 false
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ad_ip_parameter SOFT_PCS BOOLEAN false false
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ad_ip_parameter TX_OR_RX_N BOOLEAN false false
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ad_ip_parameter LANE_RATE FLOAT 10000 false
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ad_ip_parameter REFCLK_FREQUENCY FLOAT 500.0 false
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ad_ip_parameter NUM_OF_LANES POSITIVE 4 false
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ad_ip_parameter REGISTER_INPUTS INTEGER 0 false
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ad_ip_parameter LANE_INVERT INTEGER 0 false
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proc jesd204_phy_composition_callback {} {
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set soft_pcs [get_parameter_value "SOFT_PCS"]
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set tx [get_parameter_value "TX_OR_RX_N"]
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set lane_rate [get_parameter_value "LANE_RATE"]
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set refclk_frequency [get_parameter_value "REFCLK_FREQUENCY"]
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set id [get_parameter_value "ID"]
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set num_of_lanes [get_parameter_value "NUM_OF_LANES"]
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set register_inputs [get_parameter_value "REGISTER_INPUTS"]
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set lane_invert [get_parameter_value "LANE_INVERT"]
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set link_clk_frequency [expr $lane_rate / 40]
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add_instance link_clock clock_source
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set_instance_parameter_value link_clock {clockFrequency} [expr $link_clk_frequency*1000000]
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add_interface link_clk clock sink
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set_interface_property link_clk EXPORT_OF link_clock.clk_in
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add_interface link_reset reset sink
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set_interface_property link_reset EXPORT_OF link_clock.clk_in_reset
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add_instance native_phy altera_xcvr_native_a10
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set_instance_property native_phy SUPPRESS_ALL_WARNINGS true
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set_instance_property native_phy SUPPRESS_ALL_INFO_MESSAGES true
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if {$soft_pcs} {
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set_instance_parameter_value native_phy {protocol_mode} "basic_enh"
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} else {
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set_instance_parameter_value native_phy {protocol_mode} "basic_std"
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set_instance_parameter_value native_phy {std_pcs_pma_width} 20
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if {$tx} {
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set_instance_parameter_value native_phy {std_tx_byte_ser_mode} "Serialize x2"
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set_instance_parameter_value native_phy {std_tx_8b10b_enable} 1
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set_instance_parameter_value native_phy {std_tx_polinv_enable} 1
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set_instance_parameter_value native_phy {enable_port_tx_polinv} 1
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} else {
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set_instance_parameter_value native_phy {std_rx_byte_deser_mode} "Deserialize x2"
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set_instance_parameter_value native_phy {std_rx_8b10b_enable} 1
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set_instance_parameter_value native_phy {std_rx_word_aligner_mode} "manual (PLD controlled)"
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set_instance_parameter_value native_phy {std_rx_word_aligner_pattern_len} 20
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set_instance_parameter_value native_phy {std_rx_word_aligner_pattern} 0xA0D7C
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set_instance_parameter_value native_phy {enable_port_rx_std_wa_patternalign} 1
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set_instance_parameter_value native_phy {std_rx_polinv_enable} 1
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set_instance_parameter_value native_phy {enable_port_rx_polinv} 1
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}
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}
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if {$tx} {
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set_instance_parameter_value native_phy {duplex_mode} "tx"
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set_instance_parameter_value native_phy {bonded_mode} "not_bonded"
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set_instance_parameter_value native_phy {enable_port_tx_pma_elecidle} 0
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set_instance_parameter_value native_phy {enh_txfifo_mode} "Phase compensation"
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} else {
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set_instance_parameter_value native_phy {duplex_mode} "rx"
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set_instance_parameter_value native_phy {set_cdr_refclk_freq} $refclk_frequency
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set_instance_parameter_value native_phy {enable_port_rx_is_lockedtodata} 1
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set_instance_parameter_value native_phy {enable_port_rx_is_lockedtoref} 0
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set_instance_parameter_value native_phy {enable_ports_rx_manual_cdr_mode} 0
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set_instance_parameter_value native_phy {enh_rxfifo_mode} "Phase compensation"
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}
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set_instance_parameter_value native_phy {channels} $num_of_lanes
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set_instance_parameter_value native_phy {set_data_rate} $lane_rate
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set_instance_parameter_value native_phy {enable_simple_interface} 1
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set_instance_parameter_value native_phy {enh_pcs_pma_width} 40
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set_instance_parameter_value native_phy {enh_pld_pcs_width} 40
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set_instance_parameter_value native_phy {rcfg_enable} 1
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set_instance_parameter_value native_phy {rcfg_shared} 0
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set_instance_parameter_value native_phy {rcfg_jtag_enable} 0
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set_instance_parameter_value native_phy {rcfg_sv_file_enable} 0
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set_instance_parameter_value native_phy {rcfg_h_file_enable} 0
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set_instance_parameter_value native_phy {rcfg_mif_file_enable} 0
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set_instance_parameter_value native_phy {set_user_identifier} $id
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set_instance_parameter_value native_phy {set_capability_reg_enable} 1
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set_instance_parameter_value native_phy {set_csr_soft_logic_enable} 1
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set_instance_parameter_value native_phy {set_prbs_soft_logic_enable} 0
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add_instance phy_glue jesd204_phy_glue
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set_instance_parameter_value phy_glue TX_OR_RX_N $tx
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set_instance_parameter_value phy_glue SOFT_PCS $soft_pcs
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set_instance_parameter_value phy_glue NUM_OF_LANES $num_of_lanes
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set_instance_parameter_value phy_glue LANE_INVERT $lane_invert
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add_interface reconfig_clk clock sink
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set_interface_property reconfig_clk EXPORT_OF phy_glue.reconfig_clk
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add_interface reconfig_reset reset sink
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set_interface_property reconfig_reset EXPORT_OF phy_glue.reconfig_reset
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if {$tx} {
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add_interface serial_clk hssi_serial_clock end
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set_interface_property serial_clk EXPORT_OF phy_glue.tx_serial_clk0
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add_connection link_clock.clk phy_glue.tx_coreclkin
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if {$soft_pcs} {
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add_connection phy_glue.phy_tx_enh_data_valid native_phy.tx_enh_data_valid
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}
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foreach x {reconfig_clk reconfig_reset reconfig_avmm tx_coreclkin \
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tx_clkout tx_serial_clk0 tx_parallel_data unused_tx_parallel_data} {
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add_connection phy_glue.phy_${x} native_phy.${x}
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}
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foreach x {serial_data analogreset digitalreset cal_busy} {
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add_interface ${x} conduit end
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set_interface_property ${x} EXPORT_OF native_phy.tx_${x}
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}
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if {$soft_pcs == false} {
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add_connection phy_glue.phy_tx_datak native_phy.tx_datak
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add_connection phy_glue.phy_tx_polinv native_phy.tx_polinv
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}
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} else {
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add_interface ref_clk clock sink
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set_interface_property ref_clk EXPORT_OF phy_glue.rx_cdr_refclk0
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add_connection link_clock.clk phy_glue.rx_coreclkin
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foreach x {serial_data analogreset digitalreset cal_busy is_lockedtodata} {
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add_interface ${x} conduit end
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set_interface_property ${x} EXPORT_OF native_phy.rx_${x}
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}
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foreach x {reconfig_clk reconfig_reset reconfig_avmm rx_coreclkin \
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rx_clkout rx_parallel_data rx_cdr_refclk0} {
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add_connection phy_glue.phy_${x} native_phy.${x}
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}
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if {$soft_pcs == false} {
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foreach x {rx_datak rx_disperr rx_errdetect rx_std_wa_patternalign} {
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add_connection phy_glue.phy_${x} native_phy.${x}
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}
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add_connection phy_glue.phy_rx_polinv native_phy.rx_polinv
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}
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}
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for {set i 0} {$i < $num_of_lanes} {incr i} {
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add_interface reconfig_avmm_${i} avalon slave
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set_interface_property reconfig_avmm_${i} EXPORT_OF phy_glue.reconfig_avmm_${i}
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add_interface phy_${i} conduit start
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if {$tx} {
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if {$soft_pcs} {
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add_instance soft_pcs_${i} jesd204_soft_pcs_tx
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set_instance_parameter_value soft_pcs_${i} INVERT_OUTPUTS \
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[expr ($lane_invert >> $i) & 1]
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add_connection link_clock.clk soft_pcs_${i}.clock
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add_connection link_clock.clk_reset soft_pcs_${i}.reset
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add_connection soft_pcs_${i}.tx_raw_data phy_glue.tx_raw_data_${i}
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set_interface_property phy_${i} EXPORT_OF soft_pcs_${i}.tx_phy
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} else {
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set_interface_property phy_${i} EXPORT_OF phy_glue.tx_phy_${i}
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}
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} else {
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if {$soft_pcs} {
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add_instance soft_pcs_${i} jesd204_soft_pcs_rx
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set_instance_parameter_value soft_pcs_${i} REGISTER_INPUTS $register_inputs
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set_instance_parameter_value soft_pcs_${i} INVERT_INPUTS \
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[expr ($lane_invert >> $i) & 1]
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add_connection link_clock.clk soft_pcs_${i}.clock
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add_connection link_clock.clk_reset soft_pcs_${i}.reset
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add_connection phy_glue.rx_raw_data_${i} soft_pcs_${i}.rx_raw_data
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set_interface_property phy_${i} EXPORT_OF soft_pcs_${i}.rx_phy
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} else {
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set_interface_property phy_${i} EXPORT_OF phy_glue.rx_phy_${i}
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}
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}
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}
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}
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