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pluto_hdl_adi/library/axi_dmac
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Laszlo Nagy ef4ceac6fc axi_dmac: Reduce the width of ID signals to minimum 
Reduce the width of ID signals to avoid size mismatches in Arria 10 SoC
projects where the ID width of the hard IP is 4.
The width of ID that reaches the slave can be increased by the interconnect if
multiple masters access the slave so we end up with mismatches.

Since these signals are unused it is safe to reduce them to minimum width and
let the interconnect zero-extend them as required.
 		2018-08-21 14:08:14 +03:00
..
bd axi_dmac: fix address width detection 2018-07-20 18:12:24 +03:00
tb axi_dmac: Enforce transfer length and stride alignments 2018-07-03 13:44:34 +02:00
2d_transfer.v axi_dmac: TLAST support for 2d transfers 2018-07-13 13:46:40 +03:00
Makefile axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
address_generator.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
axi_dmac.v axi_dmac: Reduce the width of ID signals to minimum 2018-08-21 14:08:14 +03:00
axi_dmac_burst_memory.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
axi_dmac_constr.sdc axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
axi_dmac_constr.ttcl axi_dmac: Remove unused constraint 2018-07-06 16:31:40 +03:00
axi_dmac_hw.tcl axi_dmac: Reduce the width of ID signals to minimum 2018-08-21 14:08:14 +03:00
axi_dmac_ip.tcl axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
axi_dmac_pkg_sv.ttcl axi_dmac: ttcl file support for simulation 2018-07-11 11:30:22 +03:00
axi_dmac_regmap.v axi_dmac: Enforce transfer length and stride alignments 2018-07-03 13:44:34 +02:00
axi_dmac_regmap_request.v axi_dmac: Enforce transfer length and stride alignments 2018-07-03 13:44:34 +02:00
axi_dmac_reset_manager.v axi_dmac: Rework transfer shutdown 2018-07-03 13:44:34 +02:00
axi_dmac_resize_dest.v axi_dmac: Rework data store-and-forward buffer 2018-07-03 13:44:34 +02:00
axi_dmac_resize_src.v axi_dmac: Remove backpressure from the source pipeline 2018-07-03 13:44:34 +02:00
axi_dmac_transfer.v axi_dmac: TLAST support for 2d transfers 2018-07-13 13:46:40 +03:00
axi_register_slice.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
data_mover.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
dest_axi_mm.v axi_dmac: Eliminate beat counter for the destination interfaces 2018-07-03 13:44:34 +02:00
dest_axi_stream.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
dest_fifo_inf.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
inc_id.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
request_arb.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
request_generator.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
resp.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
response_generator.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
response_handler.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
splitter.v license: Fix a spelling mistake 2018-04-11 15:09:54 +03:00
src_axi_mm.v axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
src_axi_stream.v axi_dmac: Move transfer abort logic to data mover 2018-07-03 13:44:34 +02:00
src_fifo_inf.v axi_dmac: Move transfer abort logic to data mover 2018-07-03 13:44:34 +02:00