114 lines
3.4 KiB
Verilog
114 lines
3.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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// csc = c1*d[23:16] + c2*d[15:8] + c3*d[7:0] + c4;
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module ad_csc_1 #(
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parameter DELAY_DATA_WIDTH = 16) (
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// data
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input clk,
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input [DW:0] sync,
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input [23:0] data,
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// constants
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input [16:0] C1,
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input [16:0] C2,
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input [16:0] C3,
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input [24:0] C4,
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// sync is delay matched
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output [DW:0] csc_sync_1,
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output [ 7:0] csc_data_1);
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localparam DW = DELAY_DATA_WIDTH - 1;
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// internal wires
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wire [24:0] data_1_m_s;
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wire [24:0] data_2_m_s;
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wire [24:0] data_3_m_s;
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wire [DW:0] sync_3_m_s;
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// c1*R
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ad_csc_1_mul #(.DELAY_DATA_WIDTH(1)) i_mul_c1 (
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.clk (clk),
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.data_a (C1),
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.data_b (data[23:16]),
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.data_p (data_1_m_s),
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.ddata_in (1'd0),
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.ddata_out ());
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// c2*G
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ad_csc_1_mul #(.DELAY_DATA_WIDTH(1)) i_mul_c2 (
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.clk (clk),
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.data_a (C2),
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.data_b (data[15:8]),
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.data_p (data_2_m_s),
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.ddata_in (1'd0),
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.ddata_out ());
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// c3*B
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ad_csc_1_mul #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_mul_c3 (
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.clk (clk),
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.data_a (C3),
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.data_b (data[7:0]),
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.data_p (data_3_m_s),
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.ddata_in (sync),
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.ddata_out (sync_3_m_s));
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// sum + c4
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ad_csc_1_add #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_add_c4 (
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.clk (clk),
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.data_1 (data_1_m_s),
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.data_2 (data_2_m_s),
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.data_3 (data_3_m_s),
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.data_4 (C4),
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.data_p (csc_data_1),
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.ddata_in (sync_3_m_s),
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.ddata_out (csc_sync_1));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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