Adrian Costina 9a74a40c49 util_adxcvr: Update GTH4 parameter values to work with DAQ3 at 12.33Gbps lane rate ... Left new parameters values in binary, as that's the way they are generated with the wizard, so future diff should be easier		2018-08-23 18:06:32 +03:00
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axi_adcfifo	ad_mem_asym: Improve the implementation of the asymmetric RAM	2018-08-06 17:29:05 +03:00
axi_adxcvr	Move Altera IP core dependency tracking to library Makefiles	2018-04-11 15:09:54 +03:00
axi_dacfifo	ad_mem_asym: Improve the implementation of the asymmetric RAM	2018-08-06 17:29:05 +03:00
axi_xcvrlb	Move Altera IP core dependency tracking to library Makefiles	2018-04-11 15:09:54 +03:00
common	ad_rst: All the synchronization registers have to have ASYNC_REG TRUE	2018-08-14 17:54:14 +03:00
util_adxcvr	util_adxcvr: Update GTH4 parameter values to work with DAQ3 at 12.33Gbps lane rate	2018-08-23 18:06:32 +03:00