228 lines
7.6 KiB
Verilog
228 lines
7.6 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_adcfifo_dma #(
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parameter AXI_DATA_WIDTH = 512,
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parameter DMA_DATA_WIDTH = 64,
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parameter DMA_READY_ENABLE = 1
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) (
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input axi_clk,
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input axi_drst,
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input axi_dvalid,
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input [AXI_DATA_WIDTH-1:0] axi_ddata,
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output reg axi_dready,
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input [ 3:0] axi_xfer_status,
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input dma_clk,
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output dma_wr,
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output [DMA_DATA_WIDTH-1:0] dma_wdata,
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input dma_wready,
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input dma_xfer_req,
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output [ 3:0] dma_xfer_status
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);
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localparam DMA_MEM_RATIO = AXI_DATA_WIDTH/DMA_DATA_WIDTH;
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localparam DMA_ADDRESS_WIDTH = 8;
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localparam AXI_ADDRESS_WIDTH = (DMA_MEM_RATIO == 2) ? (DMA_ADDRESS_WIDTH - 1) :
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((DMA_MEM_RATIO == 4) ? (DMA_ADDRESS_WIDTH - 2) : (DMA_ADDRESS_WIDTH - 3));
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// internal registers
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reg [AXI_ADDRESS_WIDTH-1:0] axi_waddr = 'd0;
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reg [ 2:0] axi_waddr_rel_count = 'd0;
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reg axi_waddr_rel_t = 'd0;
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reg [AXI_ADDRESS_WIDTH-1:0] axi_waddr_rel = 'd0;
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reg [ 2:0] axi_raddr_rel_t_m = 'd0;
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reg [DMA_ADDRESS_WIDTH-1:0] axi_raddr_rel = 'd0;
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reg [DMA_ADDRESS_WIDTH-1:0] axi_addr_diff = 'd0;
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reg dma_rst = 'd0;
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reg [ 2:0] dma_waddr_rel_t_m = 'd0;
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reg [AXI_ADDRESS_WIDTH-1:0] dma_waddr_rel = 'd0;
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reg dma_rd = 'd0;
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reg dma_rd_d = 'd0;
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reg [DMA_DATA_WIDTH-1:0] dma_rdata_d = 'd0;
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reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr = 'd0;
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reg [ 2:0] dma_raddr_rel_count = 'd0;
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reg dma_raddr_rel_t = 'd0;
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reg [DMA_ADDRESS_WIDTH-1:0] dma_raddr_rel = 'd0;
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// internal signals
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wire [DMA_ADDRESS_WIDTH:0] axi_addr_diff_s;
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wire axi_raddr_rel_t_s;
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wire [DMA_ADDRESS_WIDTH-1:0] axi_waddr_s;
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wire dma_waddr_rel_t_s;
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wire [DMA_ADDRESS_WIDTH-1:0] dma_waddr_rel_s;
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wire dma_wready_s;
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wire dma_rd_s;
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wire [DMA_DATA_WIDTH-1:0] dma_rdata_s;
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// write interface
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always @(posedge axi_clk) begin
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if (axi_drst == 1'b1) begin
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axi_waddr <= 'd0;
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axi_waddr_rel_count <= 'd0;
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axi_waddr_rel_t <= 'd0;
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axi_waddr_rel <= 'd0;
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end else begin
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if (axi_dvalid == 1'b1) begin
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axi_waddr <= axi_waddr + 1'b1;
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end
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axi_waddr_rel_count <= axi_waddr_rel_count + 1'b1;
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if (axi_waddr_rel_count == 3'd7) begin
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axi_waddr_rel_t <= ~axi_waddr_rel_t;
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axi_waddr_rel <= axi_waddr;
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end
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end
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end
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assign axi_addr_diff_s = {1'b1, axi_waddr_s} - axi_raddr_rel;
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assign axi_raddr_rel_t_s = axi_raddr_rel_t_m[2] ^ axi_raddr_rel_t_m[1];
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assign axi_waddr_s = (DMA_MEM_RATIO == 2) ? {axi_waddr, 1'd0} :
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((DMA_MEM_RATIO == 4) ? {axi_waddr, 2'd0} : {axi_waddr, 3'd0});
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always @(posedge axi_clk) begin
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if (axi_drst == 1'b1) begin
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axi_raddr_rel_t_m <= 'd0;
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axi_raddr_rel <= 'd0;
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axi_addr_diff <= 'd0;
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axi_dready <= 'd0;
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end else begin
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axi_raddr_rel_t_m <= {axi_raddr_rel_t_m[1:0], dma_raddr_rel_t};
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if (axi_raddr_rel_t_s == 1'b1) begin
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axi_raddr_rel <= dma_raddr_rel;
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end
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axi_addr_diff <= axi_addr_diff_s[DMA_ADDRESS_WIDTH-1:0];
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if (axi_addr_diff >= 180) begin
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axi_dready <= 1'b0;
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end else if (axi_addr_diff <= 8) begin
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axi_dready <= 1'b1;
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end
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end
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end
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// read interface
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assign dma_waddr_rel_t_s = dma_waddr_rel_t_m[2] ^ dma_waddr_rel_t_m[1];
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assign dma_waddr_rel_s = (DMA_MEM_RATIO == 2) ? {dma_waddr_rel, 1'd0} :
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((DMA_MEM_RATIO == 4) ? {dma_waddr_rel, 2'd0} : {dma_waddr_rel, 3'd0});
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always @(posedge dma_clk) begin
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if (dma_xfer_req == 1'b0) begin
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dma_rst <= 1'b1;
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dma_waddr_rel_t_m <= 'd0;
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dma_waddr_rel <= 'd0;
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end else begin
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dma_rst <= 1'b0;
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dma_waddr_rel_t_m <= {dma_waddr_rel_t_m[1:0], axi_waddr_rel_t};
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if (dma_waddr_rel_t_s == 1'b1) begin
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dma_waddr_rel <= axi_waddr_rel;
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end
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end
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end
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assign dma_wready_s = (DMA_READY_ENABLE == 0) ? 1'b1 : dma_wready;
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assign dma_rd_s = (dma_raddr == dma_waddr_rel_s) ? 1'b0 : dma_wready_s;
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always @(posedge dma_clk) begin
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if (dma_xfer_req == 1'b0) begin
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dma_rd <= 'd0;
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dma_rd_d <= 'd0;
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dma_rdata_d <= 'd0;
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dma_raddr <= 'd0;
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dma_raddr_rel_count <= 'd0;
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dma_raddr_rel_t <= 'd0;
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dma_raddr_rel <= 'd0;
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end else begin
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dma_rd <= dma_rd_s;
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dma_rd_d <= dma_rd;
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dma_rdata_d <= dma_rdata_s;
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if (dma_rd_s == 1'b1) begin
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dma_raddr <= dma_raddr + 1'b1;
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end
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dma_raddr_rel_count <= dma_raddr_rel_count + 1'b1;
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if (dma_raddr_rel_count == 3'd7) begin
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dma_raddr_rel_t <= ~dma_raddr_rel_t;
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dma_raddr_rel <= dma_raddr;
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end
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end
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end
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// instantiations
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ad_mem_asym #(
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.A_ADDRESS_WIDTH (AXI_ADDRESS_WIDTH),
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.A_DATA_WIDTH (AXI_DATA_WIDTH),
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.B_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH),
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.B_DATA_WIDTH (DMA_DATA_WIDTH)
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) i_mem_asym (
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.clka (axi_clk),
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.wea (axi_dvalid),
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.addra (axi_waddr),
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.dina (axi_ddata),
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.clkb (dma_clk),
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.reb (1'b1),
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.addrb (dma_raddr),
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.doutb (dma_rdata_s));
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ad_axis_inf_rx #(
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.DATA_WIDTH(DMA_DATA_WIDTH)
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) i_axis_inf (
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.clk (dma_clk),
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.rst (dma_rst),
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.valid (dma_rd_d),
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.last (1'd0),
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.data (dma_rdata_d),
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.inf_valid (dma_wr),
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.inf_last (),
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.inf_data (dma_wdata),
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.inf_ready (dma_wready));
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up_xfer_status #(
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.DATA_WIDTH(4)
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) i_xfer_status (
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.up_rstn (~dma_rst),
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.up_clk (dma_clk),
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.up_data_status (dma_xfer_status),
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.d_rst (axi_drst),
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.d_clk (axi_clk),
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.d_data_status (axi_xfer_status));
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endmodule
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