zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
321 Commits
1 Branch
0 Tags
23 MiB
Verilog 61.7%
Tcl 31.2%
Makefile 3.5%
VHDL 1.9%
SystemVerilog 1%
Other 0.6%
 
 
 
 
 
 
Go to file
Lars-Peter Clausen 18a506b3ca up_axi: Wait for the transaction to fully finish before releasing up_axi_access 
Wait for the master to accept the response for the current transaction
before we allow a new transaction to start.

This fixes problems in case the master is not ready to accept the response
when we make it available.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
 		2014-09-10 13:03:52 +02:00
library up_axi: Wait for the transaction to fully finish before releasing up_axi_access 2014-09-10 13:03:52 +02:00
projects fmcomms2: c5soc: Add false path between 50MHz and VGA PLL clock 2014-09-09 15:05:06 +02:00
.gitignore a5soc: increase pipeline for qsys 2014-05-04 10:38:53 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md Add a link to EngineerZone 2014-04-15 10:25:18 +03:00

README.md

hdl

Analog Devices HDL libraries and projects

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga