106 lines
2.8 KiB
Verilog
106 lines
2.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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// A simple adder/substracter width preconfigured input ports width and turn-around value
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// Output = A - B_constant or A + B_constant
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// Constraints: Awidth >= Bwidth
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`timescale 1ns/1ps
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module ad_addsub #(
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parameter A_DATA_WIDTH = 32,
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parameter B_DATA_VALUE = 32'h1,
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parameter ADD_OR_SUB_N = 0) (
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input clk,
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input [(A_DATA_WIDTH-1):0] A,
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input [(A_DATA_WIDTH-1):0] Amax,
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output reg [(A_DATA_WIDTH-1):0] out,
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input CE);
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localparam ADDER = 1;
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localparam SUBSTRACTER = 0;
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// registers
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reg [A_DATA_WIDTH:0] out_d = 'b0;
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reg [A_DATA_WIDTH:0] out_d2 = 'b0;
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reg [(A_DATA_WIDTH-1):0] A_d = 'b0;
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reg [(A_DATA_WIDTH-1):0] A_d2 = 'b0;
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reg [(A_DATA_WIDTH-1):0] Amax_d = 'b0;
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reg [(A_DATA_WIDTH-1):0] Amax_d2 = 'b0;
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// constant regs
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reg [(A_DATA_WIDTH-1):0] B_reg = B_DATA_VALUE;
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// latch the inputs
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always @(posedge clk) begin
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A_d <= A;
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A_d2 <= A_d;
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Amax_d <= Amax;
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Amax_d2 <= Amax_d;
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end
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// ADDER/SUBSTRACTER
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always @(posedge clk) begin
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if ( ADD_OR_SUB_N == ADDER ) begin
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out_d <= A_d + B_reg;
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end else begin
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out_d <= A_d - B_reg;
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end
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end
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// Resolve
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always @(posedge clk) begin
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if ( ADD_OR_SUB_N == ADDER ) begin
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if ( out_d > Amax_d2 ) begin
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out_d2 <= out_d - Amax_d2;
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end else begin
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out_d2 <= out_d;
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end
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end else begin // SUBSTRACTER
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if ( out_d[A_DATA_WIDTH] == 1'b1 ) begin
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out_d2 <= Amax_d2 + out_d;
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end else begin
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out_d2 <= out_d;
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end
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end
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end
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// output logic
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always @(posedge clk) begin
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if ( CE ) begin
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out <= out_d2;
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end else begin
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out <= 'b0;
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end
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end
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endmodule
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