90 lines
2.7 KiB
Verilog
90 lines
2.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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// Transmit HDMI, RGB to CrYCb conversion
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// The multiplication coefficients are in 1.4.12 format
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// The addition coefficients are in 1.12.12 format
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// Cr = (+112.439/256)*R + (-094.154/256)*G + (-018.285/256)*B + 128;
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// Y = (+065.738/256)*R + (+129.057/256)*G + (+025.064/256)*B + 16;
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// Cb = (-037.945/256)*R + (-074.494/256)*G + (+112.439/256)*B + 128;
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module ad_csc_RGB2CrYCb #(
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parameter DELAY_DATA_WIDTH = 16) (
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// R-G-B inputs
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input clk,
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input [DW:0] RGB_sync,
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input [23:0] RGB_data,
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// Cr-Y-Cb outputs
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output [DW:0] CrYCb_sync,
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output [23:0] CrYCb_data);
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localparam DW = DELAY_DATA_WIDTH - 1;
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// Cr (red-diff)
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ad_csc_1 #(.DELAY_DATA_WIDTH(DELAY_DATA_WIDTH)) i_csc_1_Cr (
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.clk (clk),
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.sync (RGB_sync),
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.data (RGB_data),
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.C1 (17'h00707),
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.C2 (17'h105e2),
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.C3 (17'h10124),
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.C4 (25'h0080000),
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.csc_sync_1 (CrYCb_sync),
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.csc_data_1 (CrYCb_data[23:16]));
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// Y (luma)
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ad_csc_1 #(.DELAY_DATA_WIDTH(1)) i_csc_1_Y (
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.clk (clk),
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.sync (1'd0),
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.data (RGB_data),
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.C1 (17'h0041b),
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.C2 (17'h00810),
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.C3 (17'h00191),
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.C4 (25'h0010000),
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.csc_sync_1 (),
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.csc_data_1 (CrYCb_data[15:8]));
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// Cb (blue-diff)
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ad_csc_1 #(.DELAY_DATA_WIDTH(1)) i_csc_1_Cb (
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.clk (clk),
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.sync (1'd0),
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.data (RGB_data),
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.C1 (17'h1025f),
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.C2 (17'h104a7),
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.C3 (17'h00707),
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.C4 (25'h0080000),
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.csc_sync_1 (),
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.csc_data_1 (CrYCb_data[7:0]));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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