82 lines
2.5 KiB
Verilog
82 lines
2.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ps
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module util_pulse_gen #(
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parameter PULSE_WIDTH = 7,
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parameter PULSE_PERIOD = 100000000)( // t_period * clk_freq
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input clk,
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input rstn,
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input [31:0] pulse_period,
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input pulse_period_en,
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output reg pulse
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);
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// internal registers
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reg [(PULSE_WIDTH-1):0] pulse_width_cnt = {PULSE_WIDTH{1'b1}};
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reg [31:0] pulse_period_cnt = 32'h0;
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reg [31:0] pulse_period_d = 32'b0;
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wire end_of_period_s;
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// flop the desired period
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always @(posedge clk) begin
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pulse_period_d <= (pulse_period_en) ? pulse_period : PULSE_PERIOD;
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end
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// a free running pulse generator
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always @(posedge clk) begin
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if (rstn == 1'b0) begin
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pulse_period_cnt <= 32'h0;
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end else begin
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pulse_period_cnt <= (pulse_period_cnt < pulse_period_d) ? (pulse_period_cnt + 1) : 32'b0;
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end
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end
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assign end_of_period_s = (pulse_period_cnt == (pulse_period_d - 1)) ? 1'b1 : 1'b0;
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// generate pulse with a specified width
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always @(posedge clk) begin
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if (rstn == 1'b0) begin
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pulse_width_cnt <= 0;
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pulse <= 0;
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end else begin
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pulse_width_cnt <= (pulse == 1'b1) ? pulse_width_cnt + 1 : {PULSE_WIDTH{1'h0}};
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if(end_of_period_s == 1'b1) begin
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pulse <= 1'b1;
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end else if(pulse_width_cnt == {PULSE_WIDTH{1'b1}}) begin
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pulse <= 1'b0;
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end
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end
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end
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endmodule
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