zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
774 Commits
1 Branch
0 Tags
23 MiB
Verilog 61.7%
Tcl 31.2%
Makefile 3.5%
VHDL 1.9%
SystemVerilog 1%
Other 0.6%
 
 
 
 
 
 
Go to file
Istvan Csomortani 19732d89fb plddr3: Fix the adc_dwr pulse width 
The adc_dwr signal pulse width was to long, need to be just one adc_clk cycle.
 		2014-12-09 13:51:00 +02:00
library plddr3: Fix the adc_dwr pulse width 2014-12-09 13:51:00 +02:00
projects ad9467_kc705: Fix typos. 2014-12-09 13:46:51 +02:00
.gitignore a5soc: increase pipeline for qsys 2014-05-04 10:38:53 -04:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
README.md Add a link to EngineerZone 2014-04-15 10:25:18 +03:00

README.md

hdl

Analog Devices HDL libraries and projects

First time users, it is highly recommended to go through our HDL user guide at the following url:

http://wiki.analog.com/resources/fpga/docs/hdl

For support please visit our FPGA Reference Designs Support Community on EngineerZone:

http://ez.analog.com/community/fpga