317 lines
8.5 KiB
Verilog
317 lines
8.5 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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sys_rst,
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sys_clk_p,
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sys_clk_n,
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uart_sin,
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uart_sout,
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ddr3_addr,
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ddr3_ba,
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ddr3_cas_n,
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ddr3_ck_n,
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ddr3_ck_p,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_dm,
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ddr3_dq,
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ddr3_dqs_n,
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ddr3_dqs_p,
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ddr3_odt,
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ddr3_ras_n,
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ddr3_reset_n,
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ddr3_we_n,
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phy_reset_n,
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phy_mdc,
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phy_mdio,
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phy_tx_clk,
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phy_tx_ctrl,
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phy_tx_data,
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phy_rx_clk,
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phy_rx_ctrl,
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phy_rx_data,
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fan_pwm,
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gpio_lcd,
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gpio_led,
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gpio_sw,
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iic_rstn,
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iic_scl,
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iic_sda,
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hdmi_out_clk,
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hdmi_hsync,
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hdmi_vsync,
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hdmi_data_e,
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hdmi_data,
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spdif,
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rx_clk_in_p,
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rx_clk_in_n,
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rx_frame_in_p,
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rx_frame_in_n,
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rx_data_in_p,
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rx_data_in_n,
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tx_clk_out_p,
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tx_clk_out_n,
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tx_frame_out_p,
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tx_frame_out_n,
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tx_data_out_p,
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tx_data_out_n,
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gpio_txnrx,
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gpio_enable,
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gpio_resetb,
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gpio_sync,
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gpio_en_agc,
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gpio_ctl,
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gpio_status,
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spi_csn,
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spi_clk,
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spi_mosi,
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spi_miso
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);
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input sys_rst;
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input sys_clk_p;
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input sys_clk_n;
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input uart_sin;
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output uart_sout;
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output [13:0] ddr3_addr;
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output [ 2:0] ddr3_ba;
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output ddr3_cas_n;
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output [ 0:0] ddr3_ck_n;
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output [ 0:0] ddr3_ck_p;
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output [ 0:0] ddr3_cke;
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output [ 0:0] ddr3_cs_n;
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output [ 7:0] ddr3_dm;
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inout [63:0] ddr3_dq;
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inout [ 7:0] ddr3_dqs_n;
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inout [ 7:0] ddr3_dqs_p;
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output [ 0:0] ddr3_odt;
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output ddr3_ras_n;
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output ddr3_reset_n;
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output ddr3_we_n;
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output phy_reset_n;
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output phy_mdc;
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inout phy_mdio;
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output phy_tx_clk;
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output phy_tx_ctrl;
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output [ 3:0] phy_tx_data;
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input phy_rx_clk;
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input phy_rx_ctrl;
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input [ 3:0] phy_rx_data;
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output fan_pwm;
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inout [ 6:0] gpio_lcd;
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inout [ 3:0] gpio_led;
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inout [ 8:0] gpio_sw;
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output iic_rstn;
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inout iic_scl;
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inout iic_sda;
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output hdmi_out_clk;
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output hdmi_hsync;
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output hdmi_vsync;
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output hdmi_data_e;
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output [23:0] hdmi_data;
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output spdif;
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input rx_clk_in_p;
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input rx_clk_in_n;
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input rx_frame_in_p;
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input rx_frame_in_n;
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input [ 5:0] rx_data_in_p;
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input [ 5:0] rx_data_in_n;
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output tx_clk_out_p;
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output tx_clk_out_n;
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output tx_frame_out_p;
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output tx_frame_out_n;
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output [ 5:0] tx_data_out_p;
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output [ 5:0] tx_data_out_n;
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inout gpio_txnrx;
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inout gpio_enable;
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inout gpio_resetb;
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inout gpio_sync;
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inout gpio_en_agc;
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inout [ 3:0] gpio_ctl;
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inout [ 7:0] gpio_status;
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output spi_csn;
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output spi_clk;
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output spi_mosi;
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input spi_miso;
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// internal signals
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wire [16:0] gpio_i;
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wire [16:0] gpio_o;
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wire [16:0] gpio_t;
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wire [31:0] mb_intrs;
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// instantiations
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ad_iobuf #(.DATA_WIDTH(17)) i_iobuf (
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.dt (gpio_t[16:0]),
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.di (gpio_o[16:0]),
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.do (gpio_i[16:0]),
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.dio({ gpio_txnrx,
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gpio_enable,
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gpio_resetb,
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gpio_sync,
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gpio_en_agc,
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gpio_ctl,
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gpio_status}));
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system_wrapper i_system_wrapper (
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.ddr3_addr (ddr3_addr),
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.ddr3_ba (ddr3_ba),
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.ddr3_cas_n (ddr3_cas_n),
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.ddr3_ck_n (ddr3_ck_n),
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.ddr3_ck_p (ddr3_ck_p),
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.ddr3_cke (ddr3_cke),
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.ddr3_cs_n (ddr3_cs_n),
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.ddr3_dm (ddr3_dm),
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.ddr3_dq (ddr3_dq),
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.ddr3_dqs_n (ddr3_dqs_n),
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.ddr3_dqs_p (ddr3_dqs_p),
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.ddr3_odt (ddr3_odt),
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.ddr3_ras_n (ddr3_ras_n),
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.ddr3_reset_n (ddr3_reset_n),
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.ddr3_we_n (ddr3_we_n),
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.fan_pwm (fan_pwm),
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.gpio_lcd_tri_io (gpio_lcd),
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.gpio_led_tri_io (gpio_led),
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.gpio_sw_tri_io (gpio_sw),
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.gpio_fmcomms2_i (gpio_i),
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.gpio_fmcomms2_o (gpio_o),
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.gpio_fmcomms2_t (gpio_t),
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.hdmi_data (hdmi_data),
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.hdmi_data_e (hdmi_data_e),
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.hdmi_hsync (hdmi_hsync),
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.hdmi_out_clk (hdmi_out_clk),
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.hdmi_vsync (hdmi_vsync),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.iic_rstn (iic_rstn),
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.mb_intr_10 (mb_intrs[10]),
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.mb_intr_11 (mb_intrs[11]),
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.mb_intr_12 (mb_intrs[12]),
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.mb_intr_13 (mb_intrs[13]),
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.mb_intr_14 (mb_intrs[14]),
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.mb_intr_15 (mb_intrs[15]),
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.mb_intr_16 (mb_intrs[16]),
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.mb_intr_17 (mb_intrs[17]),
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.mb_intr_18 (mb_intrs[18]),
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.mb_intr_19 (mb_intrs[19]),
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.mb_intr_20 (mb_intrs[20]),
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.mb_intr_21 (mb_intrs[21]),
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.mb_intr_22 (mb_intrs[22]),
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.mb_intr_23 (mb_intrs[23]),
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.mb_intr_24 (mb_intrs[24]),
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.mb_intr_25 (mb_intrs[25]),
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.mb_intr_26 (mb_intrs[26]),
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.mb_intr_27 (mb_intrs[27]),
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.mb_intr_28 (mb_intrs[28]),
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.mb_intr_29 (mb_intrs[29]),
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.mb_intr_30 (mb_intrs[30]),
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.mb_intr_31 (mb_intrs[31]),
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.fmcomms2_spi_irq(mb_intrs[10]),
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.fmcomms2_gpio_irq(mb_intrs[11]),
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.ad9361_adc_dma_irq (mb_intrs[12]),
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.ad9361_dac_dma_irq (mb_intrs[13]),
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.mdio_io (phy_mdio),
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.mdio_mdc (phy_mdc),
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.phy_rst_n (phy_reset_n),
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.rgmii_rd (phy_rx_data),
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.rgmii_rx_ctl (phy_rx_ctrl),
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.rgmii_rxc (phy_rx_clk),
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.rgmii_td (phy_tx_data),
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.rgmii_tx_ctl (phy_tx_ctrl),
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.rgmii_txc (phy_tx_clk),
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.spdif (spdif),
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.sys_clk_n (sys_clk_n),
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.sys_clk_p (sys_clk_p),
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.sys_rst (sys_rst),
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.spi_csn_i (1'b1),
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.spi_csn_o (spi_csn),
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.spi_miso_i (spi_miso),
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.spi_mosi_i (1'b0),
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.spi_mosi_o (spi_mosi),
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.spi_sclk_i (1'b0),
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.spi_sclk_o (spi_clk),
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.rx_clk_in_n (rx_clk_in_n),
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.rx_clk_in_p (rx_clk_in_p),
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.rx_data_in_n (rx_data_in_n),
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.rx_data_in_p (rx_data_in_p),
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.rx_frame_in_n (rx_frame_in_n),
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.rx_frame_in_p (rx_frame_in_p),
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.tx_clk_out_n (tx_clk_out_n),
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.tx_clk_out_p (tx_clk_out_p),
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.tx_data_out_n (tx_data_out_n),
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.tx_data_out_p (tx_data_out_p),
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.tx_frame_out_n (tx_frame_out_n),
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.tx_frame_out_p (tx_frame_out_p),
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.uart_sin (uart_sin),
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.uart_sout (uart_sout));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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