111 lines
3.7 KiB
Verilog
111 lines
3.7 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2015(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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//
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// Simple pulse generator for TDD control
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// The module has two modes. In function of the state of sync_mode,
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// the syncronization signal (sync_out) can get its value from an external
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// source or from its internal generator.
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//
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`timescale 1ns/1ps
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module util_tdd_sync (
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clk,
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rstn,
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sync_mode,
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sync_in,
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sync_out
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);
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input clk;
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input rstn;
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input sync_mode;
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input sync_in;
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output sync_out;
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parameter TDD_SYNC_PERIOD = 100000000;
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reg sync_mode_d1 = 1'b0;
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reg sync_mode_d2 = 1'b0;
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reg sync_out = 1'b0;
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wire sync_internal;
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wire sync_external;
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// pulse generator
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util_pulse_gen #(
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.PULSE_PERIOD(TDD_SYNC_PERIOD)
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)
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i_tdd_sync (
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.clk (clk),
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.rstn (rstn),
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.pulse (sync_internal)
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);
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// synchronization logic
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always @(posedge clk) begin
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if(rstn == 1'b0) begin
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sync_mode_d1 <= 1'b0;
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sync_mode_d2 <= 1'b0;
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end else begin
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sync_mode_d1 <= sync_mode;
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sync_mode_d2 <= sync_mode_d1;
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end
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end
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// output logic
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assign sync_external = sync_in;
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always @(posedge clk) begin
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if(rstn == 1'b0) begin
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sync_out <= 1'b0;
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end else begin
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sync_out <= (sync_mode_d2 == 1'b0) ? sync_internal : sync_external;
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end
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end
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endmodule
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