423 lines
14 KiB
Verilog
423 lines
14 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_ad5766 #(
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parameter DATA_WIDTH = 8,
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parameter NUM_OF_SDI = 1,
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parameter ASYNC_SPI_CLK = 0,
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parameter CMD_MEM_ADDRESS_WIDTH = 4,
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parameter SDO_MEM_ADDRESS_WIDTH = 4)(
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// Slave AXI interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [31:0] s_axi_awaddr,
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output s_axi_awready,
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input [ 2:0] s_axi_awprot,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [ 3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [ 1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [31:0] s_axi_araddr,
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output s_axi_arready,
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input [ 2:0] s_axi_arprot,
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output s_axi_rvalid,
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input s_axi_rready,
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output [ 1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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// FIFO transmit
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output dma_clk,
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output reg dma_valid,
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input dma_enable,
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input [15:0] dma_data,
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input dma_xfer_req,
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input dma_underflow,
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// SPI engine control interface (to the SPI engine interconnect)
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input spi_clk, // should be connected to up_clk
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input spi_resetn,
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input cmd_ready,
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output cmd_valid,
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output [15:0] cmd_data,
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input sdo_data_ready,
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output sdo_data_valid,
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output [(DATA_WIDTH-1):0] sdo_data,
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output sdi_data_ready,
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input sdi_data_valid,
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input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
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output sync_ready,
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input sync_valid,
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input [ 7:0] sync_data,
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// SPI engine offload interface (to the AXI SPI engine)
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input ctrl_clk,
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input ctrl_cmd_wr_en,
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input [15:0] ctrl_cmd_wr_data,
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input ctrl_enable,
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output ctrl_enabled,
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input ctrl_mem_reset);
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// internal wires
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wire up_wreq_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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wire up_rreq_s;
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wire [13:0] up_raddr_s;
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wire [31:0] up_rdata_s[0:1];
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wire up_rack_s[0:1];
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wire up_wack_s[0:1];
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wire trigger_s;
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wire [31:0] pulse_period_s;
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wire [15:0] dac_datarate_s;
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wire spi_reset;
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wire spi_enable_s;
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wire [ 3:0] sequencer[15:0];
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wire [ 3:0] cmd_bits;
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wire [ 3:0] end_of_sequence;
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wire spi_mem_reset_s;
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wire sequence_valid_s;
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wire [ 7:0] sequence_data_s;
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wire dac_rst_s;
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wire dac_rstn_s;
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wire [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr_next;
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// registers
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reg [31:0] up_rdata = 32'b0;
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reg up_rack = 0;
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reg up_wack = 1'b0;
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reg [15:0] cmd_mem[0:2**CMD_MEM_ADDRESS_WIDTH-1];
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reg [(DATA_WIDTH-1):0] sdo_mem[0:2**SDO_MEM_ADDRESS_WIDTH-1];
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reg [CMD_MEM_ADDRESS_WIDTH-1:0] ctrl_cmd_wr_addr = 'b0;
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reg [CMD_MEM_ADDRESS_WIDTH-1:0] spi_cmd_rd_addr = 'b0;
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reg [SDO_MEM_ADDRESS_WIDTH-1:0] ctrl_sdo_wr_addr = 'b0;
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reg [SDO_MEM_ADDRESS_WIDTH-1:0] spi_sdo_rd_addr = 'b0;
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reg spi_active = 1'b0;
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assign up_rstn = s_axi_aresetn;
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// the dma interface runs on SPI_CLK
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assign dma_clk = spi_clk;
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// command and SDO data offload
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assign cmd_valid = spi_active;
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assign cmd_data = cmd_mem[spi_cmd_rd_addr];
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assign sdo_data_valid = spi_active;
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assign sdo_data = sdo_mem[spi_sdo_rd_addr];
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assign sync_ready = 1'b1;
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assign sdi_data_ready = 1'b0;
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generate if (ASYNC_SPI_CLK) begin
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/*
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* The synchronization circuit takes care that there are no glitches on the
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* ctrl_enabled signal. ctrl_do_enable is asserted whenever ctrl_enable is
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* asserted, but only deasserted once the signal has been synchronized back from
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* the SPI domain. This makes sure that we can't end up in a state where the
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* enable signal in the SPI domain is asserted, but neither enable nor enabled
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* is asserted in the control domain.
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*/
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reg ctrl_do_enable = 1'b0;
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wire ctrl_is_enabled;
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reg spi_enabled = 1'b0;
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always @(posedge ctrl_clk) begin
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if (ctrl_enable == 1'b1) begin
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ctrl_do_enable <= 1'b1;
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end else if (ctrl_is_enabled == 1'b1) begin
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ctrl_do_enable <= 1'b0;
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end
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end
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assign ctrl_enabled = ctrl_is_enabled | ctrl_do_enable;
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always @(posedge spi_clk) begin
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spi_enabled <= spi_enable_s | spi_active;
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end
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sync_bits # (
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.NUM_OF_BITS(1),
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.ASYNC_CLK(1)
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) i_sync_enable (
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.in(ctrl_do_enable),
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.out_clk(spi_clk),
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.out_resetn(1'b1),
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.out(spi_enable_s)
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);
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sync_bits # (
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.NUM_OF_BITS(1),
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.ASYNC_CLK(1)
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) i_sync_enabled (
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.in(spi_enabled),
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.out_clk(ctrl_clk),
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.out_resetn(1'b1),
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.out(ctrl_is_enabled)
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);
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sync_bits # (
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.NUM_OF_BITS(1),
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.ASYNC_CLK(1)
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) i_sync_mem_reset (
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.in(ctrl_mem_reset),
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.out_clk(spi_clk),
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.out_resetn(1'b1),
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.out(spi_mem_reset_s)
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);
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end else begin
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assign spi_enable_s = ctrl_enable;
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assign ctrl_enabled = spi_enable_s | spi_active;
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assign spi_mem_reset_s = ctrl_mem_reset;
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end endgenerate
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assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1;
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always @(posedge spi_clk) begin
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if (spi_resetn == 1'b0) begin
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spi_active <= 1'b0;
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end else begin
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if (spi_active == 1'b0) begin
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if ((trigger_s == 1'b1 && spi_enable_s == 1'b1)) begin
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spi_active <= 1'b1;
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end
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end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin
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spi_active <= 1'b0;
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end
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end
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end
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always @(posedge spi_clk) begin
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if (cmd_valid == 1'b0) begin
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spi_cmd_rd_addr <= 'h00;
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end else if (cmd_ready == 1'b1) begin
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spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
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end
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end
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always @(posedge spi_clk) begin
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if (spi_active == 1'b0) begin
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spi_sdo_rd_addr <= 'h00;
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end else if (sdo_data_ready == 1'b1) begin
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spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
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end
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end
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always @(posedge ctrl_clk) begin
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if (ctrl_cmd_wr_en == 1'b1) begin
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cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
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end
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end
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always @(posedge ctrl_clk) begin
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if (ctrl_mem_reset == 1'b1) begin
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ctrl_cmd_wr_addr <= 0;
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end else if (ctrl_cmd_wr_en == 1'b1) begin
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ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1;
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end
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end
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// request data from the DMA at the desired rate
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always @(posedge dma_clk) begin
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if (dma_xfer_req == 1'b0) begin
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dma_valid <= 1'b0;
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end else begin
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if ((trigger_s == 1'b1) && (dma_enable == 1'b1) && (spi_enable_s == 1'b1)) begin
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dma_valid <= 1'b1;
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end
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if (dma_valid == 1'b1) begin
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dma_valid <= 1'b0;
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end
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end
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if (dma_valid == 1'b1) begin
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sdo_mem[1] <= dma_data[15:8];
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sdo_mem[2] <= dma_data[ 7:0];
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end
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if (sequence_valid_s == 1'b1) begin
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sdo_mem[0] <= sequence_data_s;
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end
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end
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// rate controller
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assign dac_rstn_s = ~dac_rst_s;
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util_pulse_gen #(.PULSE_WIDTH(1)) i_trigger_gen (
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.clk (spi_clk),
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.rstn (dac_rstn_s),
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.pulse_period (pulse_period_s),
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.pulse_period_en (1'b1),
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.pulse (trigger_s)
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);
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// offset of the sequencer registers are 8'h40
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always @(negedge up_rstn or posedge spi_clk) begin
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if (up_rstn == 1'b0) begin
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up_rdata <= 'd0;
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up_rack <= 'd0;
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up_wack <= 'd0;
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end else begin
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up_rdata <= up_rdata_s[0] | up_rdata_s[1];
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up_rack <= up_rack_s[0] | up_rack_s[1];
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up_wack <= up_wack_s[0] | up_wack_s[1];
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end
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end
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// DAC common registermap
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assign pulse_period_s = {16'h0, dac_datarate_s};
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up_ad5766_sequencer #(
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.SEQ_ID(4))
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i_sequencer (
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.sequence_clk (spi_clk),
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.sequence_rst (spi_mem_reset_s),
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.sequence_req (dma_valid),
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.sequence_valid (sequence_valid_s),
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.sequence_data (sequence_data_s),
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.up_rstn (up_rstn),
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.up_clk (spi_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[1]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[1]),
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.up_rack (up_rack_s[1]));
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up_dac_common #(
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.COMMON_ID (0)
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) i_dac_common (
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.mmcm_rst (),
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.dac_clk (spi_clk),
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.dac_rst (dac_rst_s),
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.dac_sync (),
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.dac_frame (),
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.dac_clksel (),
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.dac_par_type (),
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.dac_par_enb (),
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.dac_r1_mode (),
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.dac_datafmt (dac_datafmt),
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.dac_datarate (dac_datarate_s),
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.dac_status (),
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.dac_status_ovf (),
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.dac_status_unf (dma_underflow),
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.dac_clk_ratio (32'b0),
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.up_drp_sel (),
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.up_drp_wr (),
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.up_drp_addr (),
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.up_drp_wdata (),
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.up_drp_rdata (16'b0),
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.up_drp_ready (1'b0),
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.up_drp_locked (1'b0),
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.up_usr_chanmax (),
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.dac_usr_chanmax (8'b0),
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.up_dac_gpio_in (32'b0),
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.up_dac_gpio_out (),
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.up_rstn (up_rstn),
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.up_clk (spi_clk),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack_s[0]),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata_s[0]),
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.up_rack (up_rack_s[0]));
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// AXI wrapper
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up_axi #(
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.ADDRESS_WIDTH (14)
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) i_up_axi (
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.up_rstn (up_rstn),
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.up_clk (spi_clk),
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.up_axi_awvalid (s_axi_awvalid),
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.up_axi_awaddr (s_axi_awaddr),
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.up_axi_awready (s_axi_awready),
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.up_axi_wvalid (s_axi_wvalid),
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.up_axi_wdata (s_axi_wdata),
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.up_axi_wstrb (s_axi_wstrb),
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.up_axi_wready (s_axi_wready),
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.up_axi_bvalid (s_axi_bvalid),
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.up_axi_bresp (s_axi_bresp),
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.up_axi_bready (s_axi_bready),
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.up_axi_arvalid (s_axi_arvalid),
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.up_axi_araddr (s_axi_araddr),
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.up_axi_arready (s_axi_arready),
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.up_axi_rvalid (s_axi_rvalid),
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.up_axi_rresp (s_axi_rresp),
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.up_axi_rdata (s_axi_rdata),
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.up_axi_rready (s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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