249 lines
10 KiB
Verilog
249 lines
10 KiB
Verilog
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2013(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ns
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module prcfg_top#(
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parameter NUM_CHANNEL = 4,
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parameter ADC_EN = 1,
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parameter DAC_EN = 1) (
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input clk,
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// gpio
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input [31:0] dac_gpio_input,
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output [31:0] dac_gpio_output,
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input [31:0] adc_gpio_input,
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output [31:0] adc_gpio_output,
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// TX side
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input dma_dac_0_enable,
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output [(DBUS_WIDTH-1):0] dma_dac_0_data,
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input dma_dac_0_valid,
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input dma_dac_1_enable,
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output [(DBUS_WIDTH-1):0] dma_dac_1_data,
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input dma_dac_1_valid,
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input dma_dac_2_enable,
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output [(DBUS_WIDTH-1):0] dma_dac_2_data,
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input dma_dac_2_valid,
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input dma_dac_3_enable,
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output [(DBUS_WIDTH-1):0] dma_dac_3_data,
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input dma_dac_3_valid,
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output core_dac_0_enable,
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input [(DBUS_WIDTH-1):0] core_dac_0_data,
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output core_dac_0_valid,
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output core_dac_1_enable,
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input [(DBUS_WIDTH-1):0] core_dac_1_data,
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output core_dac_1_valid,
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output core_dac_2_enable,
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input [(DBUS_WIDTH-1):0] core_dac_2_data,
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output core_dac_2_valid,
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output core_dac_3_enable,
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input [(DBUS_WIDTH-1):0] core_dac_3_data,
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output core_dac_3_valid,
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// RX side
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input dma_adc_0_enable,
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input [(DBUS_WIDTH-1):0] dma_adc_0_data,
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input dma_adc_0_valid,
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input dma_adc_1_enable,
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input [(DBUS_WIDTH-1):0] dma_adc_1_data,
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input dma_adc_1_valid,
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input dma_adc_2_enable,
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input [(DBUS_WIDTH-1):0] dma_adc_2_data,
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input dma_adc_2_valid,
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input dma_adc_3_enable,
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input [(DBUS_WIDTH-1):0] dma_adc_3_data,
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input dma_adc_3_valid,
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output core_adc_0_enable,
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output [(DBUS_WIDTH-1):0] core_adc_0_data,
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output core_adc_0_valid,
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output core_adc_1_enable,
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output [(DBUS_WIDTH-1):0] core_adc_1_data,
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output core_adc_1_valid,
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output core_adc_2_enable,
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output [(DBUS_WIDTH-1):0] core_adc_2_data,
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output core_adc_2_valid,
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output core_adc_3_enable,
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output [(DBUS_WIDTH-1):0] core_adc_3_data,
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output core_adc_3_valid);
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localparam ENABELED = 1;
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localparam DATA_WIDTH = 16;
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localparam DBUS_WIDTH = DATA_WIDTH * NUM_CHANNEL;
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wire [31:0] adc_gpio_out_s[(NUM_CHANNEL - 1):0];
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wire [(NUM_CHANNEL - 1):0] adc_gpio_out_s_inv[31:0];
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wire [31:0] dac_gpio_out_s[(NUM_CHANNEL - 1):0];
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wire [(NUM_CHANNEL - 1):0] dac_gpio_out_s_inv[31:0];
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wire [(NUM_CHANNEL - 1):0] core_adc_enable_s;
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wire [(NUM_CHANNEL - 1):0] core_adc_valid_s;
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wire [(NUM_CHANNEL - 1):0] core_adc_data_s[15:0];
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wire [(NUM_CHANNEL - 1):0] dma_adc_enable_s;
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wire [(NUM_CHANNEL - 1):0] dma_adc_valid_s;
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wire [(NUM_CHANNEL - 1):0] dma_adc_data_s[15:0];
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wire [(NUM_CHANNEL - 1):0] core_dac_enable_s;
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wire [(NUM_CHANNEL - 1):0] core_dac_valid_s;
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wire [(NUM_CHANNEL - 1):0] core_dac_data_s[15:0];
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wire [(NUM_CHANNEL - 1):0] dma_dac_enable_s;
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wire [(NUM_CHANNEL - 1):0] dma_dac_valid_s;
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wire [(NUM_CHANNEL - 1):0] dma_dac_data_s[15:0];
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genvar l_inst;
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generate
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for(l_inst = 0; l_inst < NUM_CHANNEL; l_inst = l_inst + 1) begin: tx_rx_data_path
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if(ADC_EN == ENABELED) begin
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prcfg_adc #(
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.CHANNEL_ID(l_inst)
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) i_prcfg_adc_i (
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.clk(clk),
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.control(adc_gpio_input),
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.status(adc_gpio_out_s[l_inst]),
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.src_adc_enable(core_adc_enable_s[l_inst]),
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.src_adc_valid(core_adc_valid_s[l_inst]),
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.src_adc_data(core_adc_data_s[l_inst]),
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.dst_adc_enable(dma_adc_enable_s[l_inst]),
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.dst_adc_valid(dma_adc_valid_s[l_inst]),
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.dst_adc_data(dma_adc_data_s[l_inst])
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);
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end
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if(DAC_EN == ENABELED) begin
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prcfg_dac #(
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.CHANNEL_ID(l_inst)
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) i_prcfg_dac_i (
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.clk(clk),
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.control(dac_gpio_input),
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.status(dac_gpio_out_s[l_inst]),
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.src_dac_enable(dma_dac_enable_s[l_inst]),
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.src_dac_data(dma_dac_data_s[l_inst]),
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.src_dac_valid(dma_dac_valid_s[l_inst]),
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.dst_dac_enable(core_dac_enable_s[l_inst]),
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.dst_dac_data(core_dac_data_s[l_inst]),
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.dst_dac_valid(core_dac_valid_s[l_inst])
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);
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end
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end
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endgenerate
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genvar i;
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genvar j;
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generate
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for(i = 0; i < 32; i = i + 1) begin
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for(j = 0; j < NUM_CHANNEL; j = j + 1) begin
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assign adc_gpio_out_s_inv[i][j] = adc_gpio_out_s[j][i];
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assign dac_gpio_out_s_inv[i][j] = dac_gpio_out_s[j][i];
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end
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end
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endgenerate
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// generate gpio_outputs
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generate
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for(i = 0; i < 32; i = i + 1) begin
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assign adc_gpio_output[i] = |adc_gpio_out_s_inv[i];
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assign dac_gpio_output[i] = |dac_gpio_out_s_inv[i];
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end
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endgenerate
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// port connections
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assign core_dac_0_enable = core_dac_enable_s[0];
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assign core_dac_0_valid = core_dac_valid_s[0];
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assign core_dac_data_s[0] = core_dac_0_data;
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assign core_dac_1_enable = core_dac_enable_s[1];
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assign core_dac_1_valid = core_dac_valid_s[1];
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assign core_dac_data_s[1] = core_dac_1_data;
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assign core_dac_2_enable = core_dac_enable_s[2];
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assign core_dac_2_valid = core_dac_valid_s[2];
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assign core_dac_data_s[2] = core_dac_2_data;
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assign core_dac_3_enable = core_dac_enable_s[3];
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assign core_dac_3_valid = core_dac_valid_s[3];
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assign core_dac_data_s[3] = core_dac_3_data;
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assign dma_dac_enable_s[0] = dma_dac_0_enable;
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assign dma_dac_valid_s[0] = dma_dac_0_valid;
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assign dma_dac_0_data = dma_dac_data_s[0];
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assign dma_dac_enable_s[1] = dma_dac_1_enable;
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assign dma_dac_valid_s[1] = dma_dac_1_valid;
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assign dma_dac_1_data = dma_dac_data_s[1];
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assign dma_dac_enable_s[2] = dma_dac_2_enable;
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assign dma_dac_valid_s[2] = dma_dac_2_valid;
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assign dma_dac_2_data = dma_dac_data_s[2];
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assign dma_dac_enable_s[3] = dma_dac_3_enable;
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assign dma_dac_valid_s[3] = dma_dac_3_valid;
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assign dma_dac_3_data = dma_dac_data_s[3];
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assign core_adc_0_enable = core_adc_enable_s[0];
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assign core_adc_0_valid = core_adc_valid_s[0];
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assign core_adc_0_data = core_adc_data_s[0];
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assign core_adc_1_enable = core_adc_enable_s[1];
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assign core_adc_1_valid = core_adc_valid_s[1];
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assign core_adc_1_data = core_adc_data_s[1];
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assign core_adc_2_enable = core_adc_enable_s[2];
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assign core_adc_2_valid = core_adc_valid_s[2];
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assign core_adc_2_data = core_adc_data_s[2];
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assign core_adc_3_enable = core_adc_enable_s[3];
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assign core_adc_3_valid = core_adc_valid_s[3];
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assign core_adc_3_data = core_adc_data_s[3];
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assign dma_adc_enable_s[0] = dma_adc_0_enable;
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assign dma_adc_valid_s[0] = dma_adc_0_valid;
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assign dma_adc_data_s[0] = dma_adc_0_data;
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assign dma_adc_enable_s[1] = dma_adc_1_enable;
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assign dma_adc_valid_s[1] = dma_adc_1_valid;
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assign dma_adc_data_s[1] = dma_adc_1_data;
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assign dma_adc_enable_s[2] = dma_adc_2_enable;
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assign dma_adc_valid_s[2] = dma_adc_2_valid;
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assign dma_adc_data_s[2] = dma_adc_2_data;
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assign dma_adc_enable_s[3] = dma_adc_3_enable;
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assign dma_adc_valid_s[3] = dma_adc_3_valid;
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assign dma_adc_data_s[3] = dma_adc_3_data;
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endmodule
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