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laurent-19 1bef2bf304 projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR 
* Updated bd spi hierarchy, see library/spi_engine.tcl
 * Enabled ext_clk for PWM to use 96 MHz spi clk
 * Modified PWM channels used:
  - ch1: ODR - 850 ns period, 130 ns high time
	 ==> max fODR = 1.18 MHz
  - ch0: trigger - 850 ns period, 30 phase shift
         ==> 10 ns between falling ODR rising DCLK
 * Changed spi offload trigger signal:
  - replaced edge detect,sync_bits IPs with PWM trigger

Signed-off-by: laurent-19 <laurentiu.popa@analog.com>
 		2023-03-29 15:08:07 +03:00
..
common projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR 2023-03-29 15:08:07 +03:00
zed projects/ad7134_fmc: Update bd SPIE hierarchy, spi trigger, ODR 2023-03-29 15:08:07 +03:00
Makefile library & projects: Update Makefiles 2023-01-27 11:54:05 +02:00
Readme.md ad7134_fmc: Update Readme 2022-02-07 14:41:25 +02:00

Readme.md

AD7134-FMC HDL Project

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