pluto_hdl_adi/library/axi_ad9361
Istvan Csomortani 12c95b059d ad_tdd_control: Remove tdd_enable_synced control line
For a better timing and control, the valid control lines are gated with flops, instead of combinatorial logic.
This is the main reason why we do not need the tdd_enable_synced signal anymore. The out coming data is delayed by one clock cycle to keep data and control lines synced.
2015-12-03 11:16:28 +02:00
..
Makefile axi_ad9361: Delete the old sync generator from the core 2015-11-11 11:06:19 +02:00
axi_ad9361.v ad_tdd_control: Remove tdd_enable_synced control line 2015-12-03 11:16:28 +02:00
axi_ad9361_alt_lvds_rx.v Add .gitattributes file 2015-07-01 18:43:51 +02:00
axi_ad9361_alt_lvds_tx.v Add .gitattributes file 2015-07-01 18:43:51 +02:00
axi_ad9361_constr.xdc ad9361- ensm through dev-if 2015-08-27 11:41:49 -04:00
axi_ad9361_dev_if.v ad9361- ensm through dev-if 2015-08-27 11:41:51 -04:00
axi_ad9361_dev_if_alt.v axi_ad9361: Removed old signals from the altera device interface module 2015-11-24 11:20:35 +02:00
axi_ad9361_hw.tcl axi_ad9361: Updated altera interfaces, added FIFO conduits per channel 2015-11-24 11:21:08 +02:00
axi_ad9361_ip.tcl axi_ad9361: Delete the old sync generator from the core 2015-11-11 11:06:19 +02:00
axi_ad9361_rx.v hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
axi_ad9361_rx_channel.v hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
axi_ad9361_rx_pnmon.v hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
axi_ad9361_tdd.v ad_tdd_control: Remove tdd_enable_synced control line 2015-12-03 11:16:28 +02:00
axi_ad9361_tdd_if.v hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00
axi_ad9361_tx.v ad9361- ensm through dev-if 2015-08-27 11:41:53 -04:00
axi_ad9361_tx_channel.v hdl/library: Update the IP parameters 2015-08-19 14:11:47 +03:00