1c8f210baf
The ADI_EXTRACT_PORTS variable is used to extract all the ports and nets properties of the desired IPS for the TransceiverToolbox and HighSpeedConverterToolbox to be later used for generating the json files automatically. The ADI_SKIP_SYNTHESIS variable is used to stop the building process before the synthesis when used with Matlab support as it is not necessary at this point. The ADI_MATLAB variable is used to choose the correct paths when building the design when using the HWA workflow. |
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.. | ||
adi_board.tcl | ||
adi_fmc_constr_generator.tcl | ||
adi_intel_msg.tcl | ||
adi_make.tcl | ||
adi_make_boot_bin.tcl | ||
adi_pd.tcl | ||
adi_project_intel.tcl | ||
adi_project_xilinx.tcl | ||
adi_tquest.tcl | ||
adi_xilinx_msg.tcl | ||
gtwiz_parser.pl | ||
gtwizard_generator.tcl | ||
project-intel.mk | ||
project-toplevel.mk | ||
project-xilinx.mk |