pluto_hdl_adi/library/axi_dmac
Laszlo Nagy bc8e7881f2 axi_dmac: Hook up ID
Signed-off-by: Laszlo Nagy <laszlo.nagy@analog.com>
2022-01-25 09:50:22 +02:00
..
bd axi_dmac: generalize version check 2020-04-03 11:18:59 +03:00
tb axi_dmac: Restore axi_dmac_regmap_request to f7b8a2d version 2021-07-02 15:52:48 +03:00
2d_transfer.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
Makefile Makefile: Fix misc makefiles from projects and library 2021-10-05 14:24:48 +03:00
address_generator.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
axi_dmac.v axi_dmac: Hook up ID 2022-01-25 09:50:22 +02:00
axi_dmac_burst_memory.v axi_dmac: fix non-blocking assignment in combinatorial block 2021-03-01 09:21:59 +02:00
axi_dmac_constr.sdc axi_dmac: preparation work for reporting length of partial transfers 2018-09-07 11:38:04 +03:00
axi_dmac_constr.ttcl axi_dmac: Update IP with the new util_axis_fifo 2020-12-04 11:00:53 +02:00
axi_dmac_hw.tcl Update Quartus Prime version from 19.3.0 to 20.1.0 2021-03-08 11:29:33 +02:00
axi_dmac_ip.tcl axi_dmac: Allow wider FIFO/AXI Stream interface 2021-11-10 14:03:34 +02:00
axi_dmac_pkg_sv.ttcl axi_dmac: ttcl file support for simulation 2018-07-11 11:30:22 +03:00
axi_dmac_regmap.v axi_dmac: Add interface description register 2020-08-12 17:50:16 +03:00
axi_dmac_regmap_request.v axi_dmac: Restore axi_dmac_regmap_request to f7b8a2d version 2021-07-02 15:52:48 +03:00
axi_dmac_reset_manager.v sync_bits: Change I/O names of wires "in" and "out" for VHDL users 2019-04-23 18:03:23 +03:00
axi_dmac_resize_dest.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
axi_dmac_resize_src.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
axi_dmac_response_manager.v axi_dmac: Update IP with the new util_axis_fifo 2020-12-04 11:00:53 +02:00
axi_dmac_transfer.v axi_dmac: burst_memory: Add support for using asymmetric memory 2018-11-30 23:41:49 +02:00
axi_register_slice.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
data_mover.v axi_dmac: patch xfer_request 2019-05-24 11:11:08 +03:00
dest_axi_mm.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
dest_axi_stream.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
dest_fifo_inf.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
inc_id.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
request_arb.v axi_dmac: Update IP with the new util_axis_fifo 2020-12-04 11:00:53 +02:00
request_generator.v whitespace: Delete all trailing white spaces 2019-06-07 10:20:15 +03:00
resp.vh axi_dmac: renamed .h files to .vh 2018-07-11 11:30:22 +03:00
response_generator.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
response_handler.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
splitter.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
src_axi_mm.v axi_dmac: Remove length alignment requirement for MM interfaces 2018-11-30 23:41:49 +02:00
src_axi_stream.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00
src_fifo_inf.v Add missing timescale annotations 2018-10-17 10:32:47 +03:00