169 lines
5.5 KiB
Verilog
Executable File
169 lines
5.5 KiB
Verilog
Executable File
// ***************************************************************************
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// ***************************************************************************
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// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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// clock and resets
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input sys_clk,
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input sys_resetn,
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// ddr3
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output ddr3_clk_p,
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output ddr3_clk_n,
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output [14:0] ddr3_a,
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output [ 2:0] ddr3_ba,
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output ddr3_cke,
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output ddr3_cs_n,
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output ddr3_odt,
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output ddr3_reset_n,
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output ddr3_we_n,
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output ddr3_ras_n,
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output ddr3_cas_n,
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inout [ 7:0] ddr3_dqs_p,
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inout [ 7:0] ddr3_dqs_n,
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inout [63:0] ddr3_dq,
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output [ 7:0] ddr3_dm,
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input ddr3_rzq,
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input ddr3_ref_clk,
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// ethernet
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input eth_ref_clk,
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input eth_rxd,
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output eth_txd,
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output eth_mdc,
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inout eth_mdio,
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output eth_resetn,
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input eth_intn,
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// board gpio
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input [10:0] gpio_bd_i,
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output [15:0] gpio_bd_o,
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// flash
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output flash_oen,
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output [ 1:0] flash_cen,
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output [27:0] flash_addr,
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inout [31:0] flash_data,
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output flash_wen,
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output flash_advn,
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output flash_clk,
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output flash_resetn
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);
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// internal signals
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wire eth_reset;
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wire eth_mdio_i;
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wire eth_mdio_o;
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wire eth_mdio_t;
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [23:0] flash_addr_raw;
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// assignments
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// board stuff
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assign eth_resetn = ~eth_reset;
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assign eth_mdio_i = eth_mdio;
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assign eth_mdio = (eth_mdio_t == 1'b1) ? 1'bz : eth_mdio_o;
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assign ddr3_a[14:12] = 3'd0;
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assign gpio_i[63:32] = gpio_o[63:32];
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assign gpio_i[31:27] = gpio_o[31:27];
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assign gpio_i[26:16] = gpio_bd_i;
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assign gpio_i[15: 0] = gpio_o[15: 0];
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assign gpio_bd_o = gpio_o[15:0];
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// User code space at offset 0x0930_0000 per Intel's Board Update Portal
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// reference design used to program flash
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assign flash_addr = flash_addr_raw + 28'h9300000;
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// Common Flash interface assignments
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assign flash_resetn = 1'b1;
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assign flash_advn = 1'b0;
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assign flash_clk = 1'b0;
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assign flash_cen[1] = flash_cen[0];
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// instantiations
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system_bd i_system_bd (
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.sys_clk_clk (sys_clk),
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.sys_ddr3_cntrl_mem_mem_ck (ddr3_clk_p),
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.sys_ddr3_cntrl_mem_mem_ck_n (ddr3_clk_n),
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.sys_ddr3_cntrl_mem_mem_a (ddr3_a[11:0]),
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.sys_ddr3_cntrl_mem_mem_ba (ddr3_ba),
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.sys_ddr3_cntrl_mem_mem_cke (ddr3_cke),
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.sys_ddr3_cntrl_mem_mem_cs_n (ddr3_cs_n),
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.sys_ddr3_cntrl_mem_mem_odt (ddr3_odt),
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.sys_ddr3_cntrl_mem_mem_reset_n (ddr3_reset_n),
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.sys_ddr3_cntrl_mem_mem_we_n (ddr3_we_n),
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.sys_ddr3_cntrl_mem_mem_ras_n (ddr3_ras_n),
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.sys_ddr3_cntrl_mem_mem_cas_n (ddr3_cas_n),
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.sys_ddr3_cntrl_mem_mem_dqs (ddr3_dqs_p[7:0]),
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.sys_ddr3_cntrl_mem_mem_dqs_n (ddr3_dqs_n[7:0]),
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.sys_ddr3_cntrl_mem_mem_dq (ddr3_dq[63:0]),
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.sys_ddr3_cntrl_mem_mem_dm (ddr3_dm[7:0]),
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.sys_ddr3_cntrl_oct_oct_rzqin (ddr3_rzq),
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.sys_ddr3_cntrl_pll_ref_clk_clk (ddr3_ref_clk),
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.sys_ethernet_mdio_mdc (eth_mdc),
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.sys_ethernet_mdio_mdio_in (eth_mdio_i),
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.sys_ethernet_mdio_mdio_out (eth_mdio_o),
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.sys_ethernet_mdio_mdio_oen (eth_mdio_t),
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.sys_ethernet_ref_clk_clk (eth_ref_clk),
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.sys_ethernet_reset_reset (eth_reset),
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.sys_ethernet_sgmii_rxp_0 (eth_rxd),
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.sys_ethernet_sgmii_txp_0 (eth_txd),
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.sys_gpio_bd_in_port (gpio_i[31:0]),
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.sys_gpio_bd_out_port (gpio_o[31:0]),
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.sys_gpio_in_export (gpio_i[63:32]),
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.sys_gpio_out_export (gpio_o[63:32]),
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.pr_rom_data_nc_rom_data('h0),
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.sys_rst_reset_n (sys_resetn),
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.sys_flash_tcm_address_out (flash_addr_raw),
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.sys_flash_tcm_read_n_out (flash_oen),
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.sys_flash_tcm_write_n_out (flash_wen),
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.sys_flash_tcm_data_out (flash_data),
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.sys_flash_tcm_chipselect_n_out (flash_cen[0]));
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endmodule
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