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Istvan Csomortani 1d4b92190a fmcomms2/zc702: Fix Warning[Synth 8-2611] 
In Verilog-2001 standard, redeclaration of an output port as a wire
is not allowed.
 		2017-04-19 13:54:03 +03:00
library axi_ad9361: Fix Warning[Synth 8-2611] 2017-04-19 13:52:13 +03:00
projects fmcomms2/zc702: Fix Warning[Synth 8-2611] 2017-04-19 13:54:03 +03:00
.gitattributes Update .gitattributes 2016-02-12 14:27:35 +02:00
.gitignore Update .gitignore 2016-12-19 15:37:05 +00:00
LICENSE Update LICENSE 2014-03-11 15:06:52 -04:00
Makefile Makefile: Added top level Makefile. Modified behavior of clean and clean-all 2015-04-17 17:22:38 +03:00
README.md README.md: Update the README 2016-03-31 19:42:52 +03:00

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