1ea3ad28ae
The standard Makefile output is very noisy and it can be difficult to filter the interesting information from this noise. In quiet mode the standard Makefile output will be suppressed and instead a short human readable description of the current task is shown. E.g. > make adv7511.zed Building axi_clkgen library [library/axi_clkgen/axi_clkgen_ip.log] ... OK Building axi_hdmi_tx library [library/axi_hdmi_tx/axi_hdmi_tx_ip.log] ... OK Building axi_i2s_adi library [library/axi_i2s_adi/axi_i2s_adi_ip.log] ... OK Building axi_spdif_tx library [library/axi_spdif_tx/axi_spdif_tx_ip.log] ... OK Building util_i2c_mixer library [library/util_i2c_mixer/util_i2c_mixer_ip.log] ... OK Building adv7511_zed project [projects/adv7511/zed/adv7511_zed_vivado.log] ... OK Quiet mode is enabled by default since it generates a more human readable output. It can be disabled by passing VERBOSE=1 to make or setting the VERBOSE environment variable to 1 before calling make. E.g. > make adv7511.zed VERBOSE=1 make[1]: Entering directory 'library/axi_clkgen' rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.srcs *.hw *.sim .Xil .timestamp_altera vivado -mode batch -source axi_clkgen_ip.tcl >> axi_clkgen_ip.log 2>&1 ... Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> |
||
|---|---|---|
| library | ||
| projects | ||
| .gitattributes | ||
| .gitignore | ||
| LICENSE | ||
| LICENSE_ADIBSD | ||
| LICENSE_GPL2 | ||
| LICENSE_LGPL | ||
| Makefile | ||
| README.md | ||
| quiet.mk | ||
README.md
HDL Reference Designs
Analog Devices Inc. HDL libraries and projects.
Getting started
This repository supports reference designs for different Analog Devices boards based on Intel and Xilinx FPGA development boards or standalone.
Prerequisites
or
Please make sure that you have the required tool version.
How to build a project
For building a projects, you have to use the GNU Make tool. If you're a Windows user please checkout this page, to see how you can install this tool.
To build a project, checkout the latest release, after that just cd to the project that you want to build and run make:
[~]cd projects/fmcomms2/zc706
[~]make
A more comprehensive build guide can be found under the following link: https://wiki.analog.com/resources/fpga/docs/build
Software
In general all the projects have no-OS (baremetal) and a Linux support. See no-OS or Linux for more information.
Which branch should I use?
-
If you want to use the most stable code base, always use the latest release branch.
-
If you want to use the greatest and latest, check out the master branch.
License
In this HDL repository, there are many different and unique modules, consisting of various HDL (Verilog or VHDL) components. The individual modules are developed independently, and may be accompanied by separate and unique license terms.
The user should read each of these license terms, and understand the freedoms and responsibilities that he or she has by using this source/core.
See LICENSE for more details. The separate license files cab be found here:
Comprehensive user guide
See HDL User Guide for a more detailed guide.
Support
Feel free to ask any question at EngineerZone.