101 lines
3.4 KiB
Verilog
101 lines
3.4 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module ad_xcvr_rx_if #(
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parameter OCTETS_PER_BEAT = 4,
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parameter DW = OCTETS_PER_BEAT * 8
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) (
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// jesd interface
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input rx_clk,
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input [OCTETS_PER_BEAT-1:0] rx_ip_sof,
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input [DW-1:0] rx_ip_data,
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output reg rx_sof,
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output reg [DW-1:0] rx_data
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);
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// rx_ip_sof:
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// The input beat may contain more than one frame per clock, a sof bit is set for
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// each frame.
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// Every bit that corresponds to a octet that is at the beginning of a frame
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// the bit is set. E.g for OCTETS_PER_BEAT = 4
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// if F=1 all bits are set,
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// F=2 sof=4'b0101,
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// F=4 sof=4'b0001
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//
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// rx_ip_data:
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// The temporal ordering of the octets is from LSB to MSB,
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// this means the octet placed in the lowest 8 bits was received first,
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// the octet placed in the highest 8 bits was received last.
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// internal registers
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reg [DW-1:0] rx_ip_data_d = 'd0;
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reg [OCTETS_PER_BEAT-1:0] rx_ip_sof_hold = 'd0;
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reg [OCTETS_PER_BEAT-1:0] rx_ip_sof_d = 'd0;
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always @(posedge rx_clk) begin
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rx_ip_data_d <= rx_ip_data;
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rx_ip_sof_d <= rx_ip_sof;
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if (|rx_ip_sof) begin
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rx_ip_sof_hold <= rx_ip_sof;
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end
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rx_sof <= |rx_ip_sof_d;
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end
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wire [OCTETS_PER_BEAT*DW-1:0] rx_data_s;
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assign rx_data_s[0 +: DW] = rx_ip_data;
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generate
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genvar i;
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for (i = 1; i < OCTETS_PER_BEAT; i = i + 1) begin : g_rx_data_opt
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assign rx_data_s[i*DW +: DW] = {rx_ip_data[i*8-1 : 0], rx_ip_data_d[DW-1 : i*8]};
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end
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endgenerate
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integer j;
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always @(posedge rx_clk) begin
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for (j = OCTETS_PER_BEAT-1; j >= 0; j = j - 1) begin
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if (rx_ip_sof_hold[j] == 1'b1) begin
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rx_data <= rx_data_s[j*DW +: DW];
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end
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end
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end
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endmodule
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