134 lines
4.9 KiB
VHDL
134 lines
4.9 KiB
VHDL
-- ***************************************************************************
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-- ***************************************************************************
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-- Copyright 2013(c) Analog Devices, Inc.
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-- Author: Lars-Peter Clausen <lars-peter.clausen@analog.com>
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--
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-- All rights reserved.
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--
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-- Redistribution and use in source and binary forms, with or without modification,
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-- are permitted provided that the following conditions are met:
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-- - Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- - Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in
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-- the documentation and/or other materials provided with the
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-- distribution.
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-- - Neither the name of Analog Devices, Inc. nor the names of its
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-- contributors may be used to endorse or promote products derived
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-- from this software without specific prior written permission.
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-- - The use of this software may or may not infringe the patent rights
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-- of one or more patent holders. This license does not release you
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-- from the requirement that you obtain separate licenses from these
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-- patent holders to use this software.
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-- - Use of the software either in source or binary form, must be run
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-- on or directly connected to an Analog Devices Inc. component.
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--
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-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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-- PARTICULAR PURPOSE ARE DISCLAIMED.
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--
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-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- ***************************************************************************
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-- ***************************************************************************
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library ieee;
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use ieee.std_logic_1164.all;
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entity i2s_clkgen is
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port(
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clk : in std_logic; -- System clock
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resetn : in std_logic; -- System reset
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enable : in Boolean ; -- Enable clockgen
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tick : in std_logic;
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bclk_div_rate : in natural range 0 to 255;
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lrclk_div_rate : in natural range 0 to 255;
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bclk : out std_logic; -- Bit Clock
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lrclk : out std_logic; -- Frame Clock
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channel_sync : out std_logic;
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frame_sync : out std_logic
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);
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end i2s_clkgen;
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architecture Behavioral of i2s_clkgen is
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signal reset_int : Boolean;
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signal prev_bclk_div_rate : natural range 0 to 255;
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signal prev_lrclk_div_rate : natural range 0 to 255;
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signal bclk_count : natural range 0 to 255;
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signal lrclk_count : natural range 0 to 255;
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signal bclk_int : std_logic;
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signal lrclk_int : std_logic;
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signal lrclk_tick : Boolean;
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begin
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reset_int <= resetn = '0' or not enable;
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bclk <= bclk_int;
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lrclk <= lrclk_int;
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-----------------------------------------------------------------------------------
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-- Serial clock generation BCLK_O
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-----------------------------------------------------------------------------------
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bclk_gen: process(clk)
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begin
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if rising_edge(clk) then
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prev_bclk_div_rate <= bclk_div_rate;
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if reset_int then -- or (bclk_div_rate /= prev_bclk_div_rate) then
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bclk_int <= '1';
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bclk_count <= bclk_div_rate;
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else
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if tick = '1' then
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if bclk_count = bclk_div_rate then
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bclk_count <= 0;
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bclk_int <= not bclk_int;
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else
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bclk_count <= bclk_count + 1;
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end if;
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end if;
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end if;
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end if;
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end process bclk_gen;
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lrclk_tick <= tick = '1' and bclk_count = bclk_div_rate and bclk_int = '1';
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channel_sync <= '1' when lrclk_count = 1 else '0';
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frame_sync <= '1' when lrclk_count = 1 and lrclk_int = '0' else '0';
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-----------------------------------------------------------------------------------
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-- Frame clock generator LRCLK_O
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-----------------------------------------------------------------------------------
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lrclk_gen: process(clk)
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begin
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if rising_edge(clk) then
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prev_lrclk_div_rate <= lrclk_div_rate;
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-- Reset
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if reset_int then -- or lrclk_div_rate /= prev_lrclk_div_rate then
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lrclk_int <= '1';
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lrclk_count <= lrclk_div_rate;
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else
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if lrclk_tick then
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if lrclk_count = lrclk_div_rate then
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lrclk_count <= 0;
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lrclk_int <= not lrclk_int;
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else
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lrclk_count <= lrclk_count + 1;
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end if;
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end if;
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end if;
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end if;
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end process lrclk_gen;
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end Behavioral;
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