537 lines
17 KiB
Verilog
537 lines
17 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module util_adc_pack (
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clk,
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chan_enable_0,
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chan_valid_0,
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chan_data_0,
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chan_enable_1,
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chan_valid_1,
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chan_data_1,
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chan_enable_2,
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chan_valid_2,
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chan_data_2,
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chan_enable_3,
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chan_valid_3,
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chan_data_3,
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chan_enable_4,
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chan_valid_4,
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chan_data_4,
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chan_enable_5,
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chan_valid_5,
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chan_data_5,
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chan_enable_6,
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chan_valid_6,
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chan_data_6,
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chan_enable_7,
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chan_valid_7,
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chan_data_7,
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ddata,
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dvalid,
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dsync
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);
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parameter NUM_OF_CHANNELS = 8; // valid values are 4 and 8
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parameter DATA_WIDTH = 16; // valid values are 16 and 32
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// common clock
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input clk;
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input chan_enable_0;
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input chan_valid_0;
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input [(DATA_WIDTH-1):0] chan_data_0;
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input chan_enable_1;
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input chan_valid_1;
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input [(DATA_WIDTH-1):0] chan_data_1;
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input chan_enable_2;
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input chan_valid_2;
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input [(DATA_WIDTH-1):0] chan_data_2;
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input chan_enable_3;
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input chan_valid_3;
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input [(DATA_WIDTH-1):0] chan_data_3;
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input chan_enable_4;
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input chan_valid_4;
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input [(DATA_WIDTH-1):0] chan_data_4;
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input chan_enable_5;
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input chan_valid_5;
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input [(DATA_WIDTH-1):0] chan_data_5;
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input chan_enable_6;
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input chan_valid_6;
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input [(DATA_WIDTH-1):0] chan_data_6;
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input chan_valid_7;
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input chan_enable_7;
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input [(DATA_WIDTH-1):0] chan_data_7;
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output [(DATA_WIDTH*NUM_OF_CHANNELS-1):0] ddata;
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output dvalid;
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output dsync;
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reg [(DATA_WIDTH*NUM_OF_CHANNELS-1):0] packed_data = 0;
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reg [(DATA_WIDTH*NUM_OF_CHANNELS-1):0] temp_data_0 = 0;
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reg [(DATA_WIDTH*NUM_OF_CHANNELS-1):0] temp_data_1 = 0;
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reg [3:0] enable_cnt;
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reg [2:0] enable_cnt_0;
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reg [2:0] enable_cnt_1;
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reg [7:0] path_enabled = 0;
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reg [7:0] path_enabled_d1 = 0;
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reg [6:0] counter_0 = 0;
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reg [7:0] en1 = 0;
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reg [7:0] en2 = 0;
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reg [7:0] en4 = 0;
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reg dvalid = 0;
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reg [(DATA_WIDTH*NUM_OF_CHANNELS-1):0] ddata = 0;
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reg [(DATA_WIDTH-1):0] chan_data_0_r;
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reg [(DATA_WIDTH-1):0] chan_data_1_r;
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reg [(DATA_WIDTH-1):0] chan_data_2_r;
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reg [(DATA_WIDTH-1):0] chan_data_3_r;
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reg [(DATA_WIDTH-1):0] chan_data_4_r;
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reg [(DATA_WIDTH-1):0] chan_data_5_r;
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reg [(DATA_WIDTH-1):0] chan_data_6_r;
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reg [(DATA_WIDTH-1):0] chan_data_7_r;
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wire chan_valid;
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assign dsync = dvalid;
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assign chan_valid = chan_valid_0 | chan_valid_1 | chan_valid_2 | chan_valid_3 | chan_valid_4 | chan_valid_5 | chan_valid_6 | chan_valid_7 ;
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always @(posedge clk)
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begin
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enable_cnt = enable_cnt_0 + enable_cnt_1;
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enable_cnt_0 = chan_enable_0 + chan_enable_1 + chan_enable_2 + chan_enable_3;
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if (NUM_OF_CHANNELS == 8)
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begin
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enable_cnt_1 = chan_enable_4 + chan_enable_5 + chan_enable_6 + chan_enable_7;
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end
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else
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begin
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enable_cnt_1 = 0;
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end
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end
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always @(posedge clk)
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begin
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if(chan_valid == 1'b1)
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begin
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chan_data_0_r <= chan_data_0;
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chan_data_1_r <= chan_data_1;
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chan_data_2_r <= chan_data_2;
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chan_data_3_r <= chan_data_3;
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chan_data_4_r <= chan_data_4;
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chan_data_5_r <= chan_data_5;
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chan_data_6_r <= chan_data_6;
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chan_data_7_r <= chan_data_7;
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end
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end
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always @(chan_data_0_r, chan_data_1_r, chan_data_2_r, chan_data_3_r, chan_enable_0, chan_enable_1, chan_enable_2, chan_enable_3 )
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begin
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casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
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4'bxxx1: temp_data_0[(DATA_WIDTH-1):0] = chan_data_0_r;
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4'bxx10: temp_data_0[(DATA_WIDTH-1):0] = chan_data_1_r;
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4'bx100: temp_data_0[(DATA_WIDTH-1):0] = chan_data_2_r;
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4'b1000: temp_data_0[(DATA_WIDTH-1):0] = chan_data_3_r;
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default: temp_data_0 [(DATA_WIDTH-1):0] = 0;
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endcase
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casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
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4'bxx11: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_1_r;
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4'bx110: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_2_r;
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4'bx101: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_2_r;
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4'b1001: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r;
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4'b1010: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r;
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4'b1100: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_3_r;
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default: temp_data_0[2*DATA_WIDTH-1:DATA_WIDTH] = 0;
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endcase
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casex ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
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4'bx111: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_2_r;
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4'b1011: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r;
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4'b1101: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r;
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4'b1110: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_3_r;
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default: temp_data_0[3*DATA_WIDTH-1:2*DATA_WIDTH] = 0;
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endcase
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case ({chan_enable_3,chan_enable_2,chan_enable_1,chan_enable_0})
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4'b1111: temp_data_0[4*DATA_WIDTH-1:3*DATA_WIDTH] = chan_data_3_r;
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default: temp_data_0[4*DATA_WIDTH-1:3*DATA_WIDTH] = 0;
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endcase
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end
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always @(chan_data_4_r, chan_data_5_r, chan_data_6_r, chan_data_7_r, chan_enable_4, chan_enable_5, chan_enable_6, chan_enable_7)
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begin
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casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4})
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4'bxxx1: temp_data_1[(DATA_WIDTH-1):0] = chan_data_4_r;
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4'bxx10: temp_data_1[(DATA_WIDTH-1):0] = chan_data_5_r;
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4'bx100: temp_data_1[(DATA_WIDTH-1):0] = chan_data_6_r;
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4'b1000: temp_data_1[(DATA_WIDTH-1):0] = chan_data_7_r;
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default: temp_data_1[(DATA_WIDTH-1):0] = 0;
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endcase
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casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4})
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4'bxx11: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_5_r;
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4'bx110: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_6_r;
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4'bx101: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_6_r;
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4'b1001: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r;
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4'b1010: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r;
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4'b1100: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = chan_data_7_r;
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default: temp_data_1[2*DATA_WIDTH-1:DATA_WIDTH] = 0;
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endcase
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casex ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4})
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4'bx111: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_6_r;
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4'b1011: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r;
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4'b1101: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r;
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4'b1110: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = chan_data_7_r;
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default: temp_data_1[3*DATA_WIDTH-1:2*DATA_WIDTH] = 0;
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endcase
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case ({chan_enable_7,chan_enable_6,chan_enable_5,chan_enable_4})
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4'b1111: temp_data_1[4*DATA_WIDTH-1:3*DATA_WIDTH] = chan_data_7_r;
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default: temp_data_1[4*DATA_WIDTH-1:3*DATA_WIDTH] = 0;
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endcase
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end
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always @(enable_cnt)
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begin
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case(enable_cnt)
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4'h1: path_enabled = 8'h01;
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4'h2: path_enabled = 8'h02;
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4'h4: path_enabled = 8'h08;
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4'h8: path_enabled = 8'h80;
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default: path_enabled = 8'h0;
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endcase
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end
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always @(temp_data_0, temp_data_1, enable_cnt_0)
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begin
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packed_data = temp_data_0 | temp_data_1 << (enable_cnt_0 * DATA_WIDTH);
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end
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always @(counter_0, path_enabled)
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begin
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case (counter_0)
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0:
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begin
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en1 = path_enabled[0];
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en2 = {2{path_enabled[1]}};
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en4 = {4{path_enabled[3]}};
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end
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1:
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begin
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en1 = path_enabled[0] << 1;
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en2 = {2{path_enabled[1]}} << 0;
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en4 = {4{path_enabled[3]}} << 0;
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end
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2:
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begin
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en1 = path_enabled[0] << 2;
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en2 = {2{path_enabled[1]}} << 2;
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en4 = {4{path_enabled[3]}} << 0;
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end
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3:
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begin
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en1 = path_enabled[0] << 3;
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en2 = {2{path_enabled[1]}} << 2;
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en4 = {4{path_enabled[3]}} << 0;
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end
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4:
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begin
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if (NUM_OF_CHANNELS == 8)
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begin
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en1 = path_enabled[0] << 4;
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en2 = {2{path_enabled[1]}} << 4;
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en4 = {4{path_enabled[3]}} << 4;
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end
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else
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begin
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en1 = path_enabled[0];
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en2 = {2{path_enabled[1]}};
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en4 = {4{path_enabled[3]}};
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end
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end
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5:
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begin
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en1 = path_enabled[0] << 5;
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en2 = {2{path_enabled[1]}} << 4;
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en4 = {4{path_enabled[3]}} << 4;
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end
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6:
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begin
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en1 = path_enabled[0] << 6;
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en2 = {2{path_enabled[1]}} << 6;
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en4 = {4{path_enabled[3]}} << 4;
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end
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7:
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begin
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en1 = path_enabled[0] << 7;
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en2 = {2{path_enabled[1]}} << 6;
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en4 = {4{path_enabled[3]}} << 4;
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end
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8:
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begin
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en1 = path_enabled[0] << 0;
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en2 = {2{path_enabled[1]}} << 0;
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en4 = {4{path_enabled[3]}} << 0;
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end
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default:
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begin
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en1 = 8'h0;
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en2 = 8'h0;
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en4 = 8'h0;
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end
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endcase
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end
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always @(posedge clk)
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begin
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path_enabled_d1 <= path_enabled;
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if (path_enabled == 8'h0 || path_enabled_d1 != path_enabled )
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begin
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counter_0 <= 7'h0;
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end
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else
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begin
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if( chan_valid == 1'b1)
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begin
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if (counter_0 > (NUM_OF_CHANNELS - 1) )
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begin
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counter_0 <= counter_0 - NUM_OF_CHANNELS + enable_cnt;
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end
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else
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begin
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counter_0 <= counter_0 + enable_cnt;
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end
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if ((counter_0 == (NUM_OF_CHANNELS - enable_cnt)) || (path_enabled == (8'h1 << (NUM_OF_CHANNELS - 1)) ))
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begin
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dvalid <= 1'b1;
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end
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else
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begin
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dvalid <= 1'b0;
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end
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end
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else
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begin
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dvalid <= 1'b0;
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end
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end
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end
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generate
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// 8 NUM_OF_CHANNELS
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if ( NUM_OF_CHANNELS == 8 )
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begin
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// FIRST FOUR NUM_OF_CHANNELS
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always @(posedge clk)
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begin
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// ddata 0
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if ((en1[0] | en2[0] | en4[0] | path_enabled[NUM_OF_CHANNELS-1]) == 1'b1)
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begin
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ddata[(DATA_WIDTH-1):0] <= packed_data[(DATA_WIDTH-1):0];
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end
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// ddata 1
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if( en1[1] == 1'b1)
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begin
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ddata[2*DATA_WIDTH-1:DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
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end
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if ( (en2[1] | en4[1] | path_enabled[NUM_OF_CHANNELS-1]) == 1'b1)
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begin
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ddata[2*DATA_WIDTH-1:DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH];
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end
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// ddata 2
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if ((en1[2] | en2[2]) == 1'b1)
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begin
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ddata[3*DATA_WIDTH-1:2*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
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end
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if ((en4[2] | path_enabled[NUM_OF_CHANNELS-1]) == 1'b1)
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begin
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ddata[3*DATA_WIDTH-1:2*DATA_WIDTH] <= packed_data[3*DATA_WIDTH-1:2*DATA_WIDTH];
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end
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// ddata 3
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if (en1[3] == 1'b1)
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begin
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ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
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end
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if (en2[3] == 1'b1)
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begin
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ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH];
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end
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if ((en4[3] | path_enabled[NUM_OF_CHANNELS-1]) == 1'b1)
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begin
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ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[4*DATA_WIDTH-1:3*DATA_WIDTH];
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end
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// ddata 4
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if ((en1[4] | en2[4] | en4[4]) == 1'b1)
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begin
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ddata[5*DATA_WIDTH-1:4*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
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end
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if (path_enabled[NUM_OF_CHANNELS-1] == 1'b1)
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begin
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ddata[5*DATA_WIDTH-1:4*DATA_WIDTH] <= packed_data[5*DATA_WIDTH-1:4*DATA_WIDTH];
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end
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// ddata 5
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if (en1[5] == 1'b1)
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begin
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ddata[6*DATA_WIDTH-1:5*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
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end
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if ((en2[5] | en4[5]) == 1'b1)
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begin
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ddata[6*DATA_WIDTH-1:5*DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH];
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end
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if (path_enabled[NUM_OF_CHANNELS-1] == 1'b1)
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begin
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ddata[6*DATA_WIDTH-1:5*DATA_WIDTH] <= packed_data[6*DATA_WIDTH-1:5*DATA_WIDTH];
|
|
end
|
|
|
|
// ddata 6
|
|
if ((en1[6] | en2[6]) == 1'b1)
|
|
begin
|
|
ddata[7*DATA_WIDTH-1:6*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
|
|
end
|
|
if (en4[6] == 1'b1)
|
|
begin
|
|
ddata[7*DATA_WIDTH-1:6*DATA_WIDTH] <= packed_data[3*DATA_WIDTH-1:2*DATA_WIDTH];
|
|
end
|
|
if (path_enabled[NUM_OF_CHANNELS-1] == 1'b1)
|
|
begin
|
|
ddata[7*DATA_WIDTH-1:6*DATA_WIDTH] <= packed_data[7*DATA_WIDTH-1:6*DATA_WIDTH];
|
|
end
|
|
|
|
// ddata 7
|
|
if (en1[7] == 1'b1)
|
|
begin
|
|
ddata[8*DATA_WIDTH-1:7*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
|
|
end
|
|
if (en2[7] == 1'b1)
|
|
begin
|
|
ddata[8*DATA_WIDTH-1:7*DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH];
|
|
end
|
|
if (en4[7] == 1'b1)
|
|
begin
|
|
ddata[8*DATA_WIDTH-1:7*DATA_WIDTH] <= packed_data[4*DATA_WIDTH-1:3*DATA_WIDTH];
|
|
end
|
|
if (path_enabled[NUM_OF_CHANNELS-1] == 1'b1)
|
|
begin
|
|
ddata[8*DATA_WIDTH-1:7*DATA_WIDTH] <= packed_data[8*DATA_WIDTH-1:7*DATA_WIDTH];
|
|
end
|
|
end
|
|
end
|
|
else
|
|
begin
|
|
always @(posedge clk)
|
|
begin
|
|
// ddata 0
|
|
if ((en1[0] | en2[0] | path_enabled[3] ) == 1'b1)
|
|
begin
|
|
ddata[(DATA_WIDTH-1):0] <= packed_data[(DATA_WIDTH-1):0];
|
|
end
|
|
|
|
// ddata 1
|
|
if( en1[1] == 1'b1)
|
|
begin
|
|
ddata[2*DATA_WIDTH-1:DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
|
|
end
|
|
if ( (en2[1] | | path_enabled[3] )== 1'b1)
|
|
begin
|
|
ddata[2*DATA_WIDTH-1:DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH];
|
|
end
|
|
|
|
// ddata 2
|
|
if ((en1[2] | en2[2]) == 1'b1)
|
|
begin
|
|
ddata[3*DATA_WIDTH-1:2*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
|
|
end
|
|
if (( path_enabled[3]) == 1'b1)
|
|
begin
|
|
ddata[3*DATA_WIDTH-1:2*DATA_WIDTH] <= packed_data[3*DATA_WIDTH-1:2*DATA_WIDTH];
|
|
end
|
|
|
|
// ddata 3
|
|
if (en1[3] == 1'b1)
|
|
begin
|
|
ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[(DATA_WIDTH-1):0];
|
|
end
|
|
if (en2[3] == 1'b1)
|
|
begin
|
|
ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[2*DATA_WIDTH-1:DATA_WIDTH];
|
|
end
|
|
if (path_enabled[3] == 1'b1)
|
|
begin
|
|
ddata[4*DATA_WIDTH-1:3*DATA_WIDTH] <= packed_data[4*DATA_WIDTH-1:3*DATA_WIDTH];
|
|
end
|
|
|
|
end
|
|
end
|
|
endgenerate
|
|
|
|
endmodule
|
|
|
|
// ***************************************************************************
|
|
// ***************************************************************************
|