1648 lines
84 KiB
XML
1648 lines
84 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<system name="$${FILENAME}">
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<component
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name="$${FILENAME}"
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displayName="$${FILENAME}"
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version="1.0"
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description=""
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tags=""
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categories="System" />
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<parameter name="bonusData"><![CDATA[bonusData
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{
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element a10gx_system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element arria10_hps_0
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{
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datum _sortIndex
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{
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value = "4";
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type = "int";
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}
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}
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element emif_a10_hps_0
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{
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datum _sortIndex
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{
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value = "5";
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type = "int";
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}
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}
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element sys_clk
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{
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datum _sortIndex
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{
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value = "0";
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type = "int";
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}
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}
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element sys_cpu_interconnect
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{
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datum _sortIndex
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{
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value = "3";
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type = "int";
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}
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}
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element sys_cpu_interconnect.s0
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{
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datum baseAddress
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{
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value = "0";
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type = "String";
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}
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}
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element sys_rst
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{
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datum _sortIndex
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{
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value = "2";
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type = "int";
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}
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}
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element sys_rst_in
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{
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datum _sortIndex
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{
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value = "1";
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type = "int";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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element system_bd
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{
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datum _originalDeviceFamily
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{
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value = "Arria 10";
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type = "String";
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}
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}
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}
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]]></parameter>
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<parameter name="clockCrossingAdapter" value="FIFO" />
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<parameter name="device" value="10AS066N3F40I2SGES" />
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<parameter name="deviceFamily" value="Arria 10" />
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<parameter name="deviceSpeedGrade" value="2" />
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<parameter name="fabricMode" value="QSYS" />
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<parameter name="generateLegacySim" value="false" />
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<parameter name="generationId" value="0" />
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<parameter name="globalResetBus" value="false" />
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<parameter name="hdlLanguage" value="VERILOG" />
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<parameter name="hideFromIPCatalog" value="false" />
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<parameter name="lockedInterfaceDefinition" value="" />
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<parameter name="maxAdditionalLatency" value="2" />
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<parameter name="projectName" value="" />
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<parameter name="sopcBorderPoints" value="false" />
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<parameter name="systemHash" value="0" />
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<parameter name="testBenchDutName" value="" />
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<parameter name="timeStamp" value="0" />
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<parameter name="useTestBenchNamingPattern" value="false" />
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<instanceScript></instanceScript>
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<interface
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name="hps_ddr"
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internal="emif_a10_hps_0.mem_conduit_end"
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type="conduit"
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dir="end" />
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<interface
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name="hps_ddr_oct"
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internal="emif_a10_hps_0.oct_conduit_end"
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type="conduit"
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dir="end" />
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<interface
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name="hps_ddr_ref_clk"
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internal="emif_a10_hps_0.pll_ref_clk_clock_sink"
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type="clock"
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dir="end" />
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<interface
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name="hps_gpio"
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internal="arria10_hps_0.h2f_gp" />
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<interface
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name="hps_io"
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internal="arria10_hps_0.hps_io"
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type="conduit"
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dir="end" />
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<interface
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name="hps_irq0"
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internal="arria10_hps_0.f2h_irq0"
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type="interrupt"
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dir="start" />
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<interface
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name="hps_irq1"
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internal="arria10_hps_0.f2h_irq1"
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type="interrupt"
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dir="start" />
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<interface name="hps_s0_axi" internal="arria10_hps_0.f2sdram0_data" />
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<interface
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name="hps_s1_axi"
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internal="arria10_hps_0.f2sdram1_data"
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type="axi"
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dir="end" />
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<interface name="hps_s2_axi" internal="arria10_hps_0.f2sdram2_data" />
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<interface
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name="hps_spi0"
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internal="arria10_hps_0.spim0"
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type="conduit"
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dir="end" />
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<interface
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name="hps_spi0_sclk"
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internal="arria10_hps_0.spim0_sclk_out"
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type="clock"
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dir="start" />
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<interface
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name="hps_spi1"
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internal="arria10_hps_0.spim1"
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type="conduit"
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dir="end" />
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<interface
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name="hps_spi1_sclk"
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internal="arria10_hps_0.spim1_sclk_out"
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type="clock"
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dir="start" />
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<interface name="sys_clk" internal="sys_clk.in_clk" type="clock" dir="end" />
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<interface
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name="sys_cpu_m_avl"
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internal="sys_cpu_interconnect.m0"
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type="avalon"
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dir="start" />
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<interface name="sys_rst" internal="sys_rst.out_reset" type="reset" dir="start" />
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<interface
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name="sys_rst_in"
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internal="sys_rst_in.in_reset"
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type="reset"
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dir="end" />
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<module
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name="arria10_hps_0"
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kind="altera_arria10_hps"
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version="15.1"
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enabled="1">
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<parameter name="AUTO_DEVICE_SPEEDGRADE" value="2" />
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<parameter name="BOOT_FROM_FPGA_Enable" value="false" />
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<parameter name="BSEL" value="1" />
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<parameter name="BSEL_EN" value="false" />
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<parameter name="CLK_EMACA_SOURCE" value="1" />
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<parameter name="CLK_EMACB_SOURCE" value="1" />
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<parameter name="CLK_EMAC_PTP_SOURCE" value="1" />
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<parameter name="CLK_GPIO_SOURCE" value="1" />
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<parameter name="CLK_HMC_PLL_SOURCE" value="0" />
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<parameter name="CLK_MAIN_PLL_SOURCE2" value="0" />
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<parameter name="CLK_MPU_CNT" value="0" />
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<parameter name="CLK_MPU_SOURCE" value="0" />
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<parameter name="CLK_NOC_CNT" value="0" />
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<parameter name="CLK_NOC_SOURCE" value="0" />
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<parameter name="CLK_PERI_PLL_SOURCE2" value="0" />
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<parameter name="CLK_S2F_USER0_SOURCE" value="0" />
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<parameter name="CLK_S2F_USER1_SOURCE" value="0" />
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<parameter name="CLK_SDMMC_SOURCE" value="1" />
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<parameter name="CM_Mode" value="N/A" />
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<parameter name="CM_PinMuxing" value="Unused" />
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<parameter name="CTI_Enable" value="false" />
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<parameter name="CUSTOM_MPU_CLK" value="800" />
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<parameter name="DEBUG_APB_Enable" value="false" />
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<parameter name="DISABLE_PERI_PLL" value="false" />
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<parameter name="DMA_Enable">No,No,No,No,No,No,No,No</parameter>
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<parameter name="EMAC0_CLK" value="250" />
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<parameter name="EMAC0_Mode" value="RGMII_with_MDIO" />
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<parameter name="EMAC0_PTP" value="false" />
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<parameter name="EMAC0_PinMuxing" value="IO" />
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<parameter name="EMAC0_SWITCH_Enable" value="false" />
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<parameter name="EMAC1_CLK" value="250" />
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<parameter name="EMAC1_Mode" value="N/A" />
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<parameter name="EMAC1_PTP" value="false" />
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<parameter name="EMAC1_PinMuxing" value="Unused" />
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<parameter name="EMAC1_SWITCH_Enable" value="false" />
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<parameter name="EMAC2_CLK" value="250" />
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<parameter name="EMAC2_Mode" value="N/A" />
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<parameter name="EMAC2_PTP" value="false" />
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<parameter name="EMAC2_PinMuxing" value="Unused" />
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<parameter name="EMAC2_SWITCH_Enable" value="false" />
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<parameter name="EMAC_PTP_REF_CLK" value="100" />
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<parameter name="EMIF_CONDUIT_Enable" value="true" />
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<parameter name="F2H_AXI_CLOCK_FREQ" value="100" />
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<parameter name="F2H_COLD_RST_Enable" value="true" />
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<parameter name="F2H_DBG_RST_Enable" value="false" />
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<parameter name="F2H_FREE_CLK_Enable" value="false" />
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<parameter name="F2H_FREE_CLK_FREQ" value="200" />
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<parameter name="F2H_SDRAM0_CLOCK_FREQ" value="100" />
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<parameter name="F2H_SDRAM1_CLOCK_FREQ" value="100" />
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<parameter name="F2H_SDRAM2_CLOCK_FREQ" value="100" />
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<parameter name="F2H_SDRAM3_CLOCK_FREQ" value="100" />
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<parameter name="F2H_SDRAM4_CLOCK_FREQ" value="100" />
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<parameter name="F2H_SDRAM5_CLOCK_FREQ" value="100" />
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<parameter name="F2H_WARM_RST_Enable" value="false" />
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<parameter name="F2SDRAM0_ENABLED" value="false" />
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<parameter name="F2SDRAM1_ENABLED" value="true" />
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<parameter name="F2SDRAM2_ENABLED" value="false" />
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<parameter name="F2SDRAM_ADDRESS_WIDTH" value="32" />
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<parameter name="F2SDRAM_PORT_CONFIG" value="5" />
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<parameter name="F2SDRAM_READY_LATENCY" value="false" />
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<parameter name="F2SINTERRUPT_Enable" value="true" />
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<parameter name="F2S_Width" value="0" />
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<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_RX_CLK_IN" value="100" />
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<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC0_TX_CLK_IN" value="100" />
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<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_RX_CLK_IN" value="100" />
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<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC1_TX_CLK_IN" value="100" />
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<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC2_RX_CLK_IN" value="100" />
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<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC2_TX_CLK_IN" value="100" />
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<parameter
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name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_EMAC_PTP_REF_CLOCK"
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value="100" />
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<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C0_SCL_IN" value="100" />
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<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2C1_SCL_IN" value="100" />
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<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC0_SCL_IN" value="100" />
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<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC1_SCL_IN" value="100" />
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<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_I2CEMAC2_SCL_IN" value="100" />
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<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SDMMC_CLK_IN" value="100" />
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<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS0_SCLK_IN" value="100" />
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<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_SPIS1_SCLK_IN" value="100" />
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<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB0_CLK_IN" value="100" />
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<parameter name="FPGA_PERIPHERAL_INPUT_CLOCK_FREQ_USB1_CLK_IN" value="100" />
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<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_GTX_CLK" value="100" />
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|
<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC0_MD_CLK" value="2.5" />
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<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_GTX_CLK" value="100" />
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<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC1_MD_CLK" value="2.5" />
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<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_GTX_CLK" value="100" />
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<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_EMAC2_MD_CLK" value="2.5" />
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<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C0_CLK" value="100" />
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<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2C1_CLK" value="100" />
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<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC0_CLK" value="100" />
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<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC1_CLK" value="100" />
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<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_I2CEMAC2_CLK" value="100" />
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<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_QSPI_SCLK_OUT" value="100" />
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<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SDMMC_CCLK" value="100" />
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<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM0_SCLK_OUT" value="100" />
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<parameter name="FPGA_PERIPHERAL_OUTPUT_CLOCK_FREQ_SPIM1_SCLK_OUT" value="100" />
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<parameter name="GPIO_REF_CLK" value="4" />
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<parameter name="GP_Enable" value="false" />
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<parameter name="H2F_AXI_CLOCK_FREQ" value="100" />
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<parameter name="H2F_COLD_RST_Enable" value="false" />
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<parameter name="H2F_CTI_CLOCK_FREQ" value="100" />
|
|
<parameter name="H2F_DEBUG_APB_CLOCK_FREQ" value="100" />
|
|
<parameter name="H2F_LW_AXI_CLOCK_FREQ" value="100000000" />
|
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<parameter name="H2F_PENDING_RST_Enable" value="false" />
|
|
<parameter name="H2F_TPIU_CLOCK_IN_FREQ" value="100" />
|
|
<parameter name="H2F_USER0_CLK_Enable" value="false" />
|
|
<parameter name="H2F_USER0_CLK_FREQ" value="400" />
|
|
<parameter name="H2F_USER1_CLK_Enable" value="false" />
|
|
<parameter name="H2F_USER1_CLK_FREQ" value="400" />
|
|
<parameter name="HMC_PLL_REF_CLK" value="800" />
|
|
<parameter name="HPS_DIV_GPIO_FREQ" value="125" />
|
|
<parameter name="HPS_IO_Enable">SDMMC:D0,SDMMC:CMD,SDMMC:CCLK,SDMMC:D1,SDMMC:D2,SDMMC:D3,NONE,NONE,SDMMC:D4,SDMMC:D5,SDMMC:D6,SDMMC:D7,UART1:TX,UART1:RX,USB0:CLK,USB0:STP,USB0:DIR,USB0:DATA0,USB0:DATA1,USB0:NXT,USB0:DATA2,USB0:DATA3,USB0:DATA4,USB0:DATA5,USB0:DATA6,USB0:DATA7,EMAC0:TX_CLK,EMAC0:TX_CTL,EMAC0:RX_CLK,EMAC0:RX_CTL,EMAC0:TXD0,EMAC0:TXD1,EMAC0:RXD0,EMAC0:RXD1,EMAC0:TXD2,EMAC0:TXD3,EMAC0:RXD2,EMAC0:RXD3,NONE,NONE,NONE,NONE,NONE,GPIO,NONE,NONE,NONE,NONE,MDIO0:MDIO,MDIO0:MDC,I2C1:SDA,I2C1:SCL,GPIO,NONE,GPIO,GPIO,NONE,NONE,NONE,NONE,NONE,NONE</parameter>
|
|
<parameter name="I2C0_Mode" value="N/A" />
|
|
<parameter name="I2C0_PinMuxing" value="Unused" />
|
|
<parameter name="I2C1_Mode" value="default" />
|
|
<parameter name="I2C1_PinMuxing" value="IO" />
|
|
<parameter name="I2CEMAC0_Mode" value="N/A" />
|
|
<parameter name="I2CEMAC0_PinMuxing" value="Unused" />
|
|
<parameter name="I2CEMAC1_Mode" value="N/A" />
|
|
<parameter name="I2CEMAC1_PinMuxing" value="Unused" />
|
|
<parameter name="I2CEMAC2_Mode" value="N/A" />
|
|
<parameter name="I2CEMAC2_PinMuxing" value="Unused" />
|
|
<parameter name="INTERNAL_OSCILLATOR_ENABLE" value="60" />
|
|
<parameter name="JTAG_Enable" value="false" />
|
|
<parameter name="L3_MAIN_FREE_CLK" value="400" />
|
|
<parameter name="L4_SYS_FREE_CLK" value="1" />
|
|
<parameter name="LWH2F_Enable" value="1" />
|
|
<parameter name="MPU_CLK_VCCL" value="0" />
|
|
<parameter name="MPU_EVENTS_Enable" value="false" />
|
|
<parameter name="NAND_Mode" value="N/A" />
|
|
<parameter name="NAND_PinMuxing" value="Unused" />
|
|
<parameter name="NOCDIV_CS_ATCLK" value="0" />
|
|
<parameter name="NOCDIV_CS_PDBGCLK" value="1" />
|
|
<parameter name="NOCDIV_CS_TRACECLK" value="0" />
|
|
<parameter name="NOCDIV_L4MAINCLK" value="0" />
|
|
<parameter name="NOCDIV_L4MPCLK" value="1" />
|
|
<parameter name="NOCDIV_L4SPCLK" value="2" />
|
|
<parameter name="OVERIDE_PERI_PLL" value="false" />
|
|
<parameter name="PERI_PLL_MANUAL_VCO_FREQ" value="2000" />
|
|
<parameter name="PLL_CLK0" value="Unused" />
|
|
<parameter name="PLL_CLK1" value="Unused" />
|
|
<parameter name="PLL_CLK2" value="Unused" />
|
|
<parameter name="PLL_CLK3" value="Unused" />
|
|
<parameter name="PLL_CLK4" value="Unused" />
|
|
<parameter name="QSPI_Mode" value="N/A" />
|
|
<parameter name="QSPI_PinMuxing" value="Unused" />
|
|
<parameter name="RUN_INTERNAL_BUILD_CHECKS" value="0" />
|
|
<parameter name="S2FINTERRUPT_CLOCKPERIPHERAL_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_CTI_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_DMA_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_EMAC0_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_EMAC1_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_EMAC2_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_FPGAMANAGER_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_GPIO_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_HMC_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_I2C0_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_I2C1_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_I2CEMAC0_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_I2CEMAC1_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_I2CEMAC2_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_L4TIMER_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_NAND_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_QSPI_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_SDMMC_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_SPIM0_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_SPIM1_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_SPIS0_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_SPIS1_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_SYSTEMMANAGER_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_SYSTIMER_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_UART0_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_UART1_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_USB0_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_USB1_Enable" value="false" />
|
|
<parameter name="S2FINTERRUPT_WATCHDOG_Enable" value="false" />
|
|
<parameter name="S2F_Width" value="0" />
|
|
<parameter name="SDMMC_Mode" value="8-bit" />
|
|
<parameter name="SDMMC_PinMuxing" value="IO" />
|
|
<parameter name="SDMMC_REF_CLK" value="200" />
|
|
<parameter name="SECURITY_MODULE_Enable" value="false" />
|
|
<parameter name="SPIM0_Mode">Single_slave_selects</parameter>
|
|
<parameter name="SPIM0_PinMuxing" value="FPGA" />
|
|
<parameter name="SPIM1_Mode">Single_slave_selects</parameter>
|
|
<parameter name="SPIM1_PinMuxing" value="FPGA" />
|
|
<parameter name="SPIS0_Mode" value="N/A" />
|
|
<parameter name="SPIS0_PinMuxing" value="Unused" />
|
|
<parameter name="SPIS1_Mode" value="N/A" />
|
|
<parameter name="SPIS1_PinMuxing" value="Unused" />
|
|
<parameter name="STM_Enable" value="false" />
|
|
<parameter name="TESTIOCTRL_DEBUGCLKSEL" value="16" />
|
|
<parameter name="TESTIOCTRL_MAINCLKSEL" value="8" />
|
|
<parameter name="TESTIOCTRL_PERICLKSEL" value="8" />
|
|
<parameter name="TEST_Enable" value="false" />
|
|
<parameter name="TRACE_Mode" value="N/A" />
|
|
<parameter name="TRACE_PinMuxing" value="Unused" />
|
|
<parameter name="UART0_Mode" value="N/A" />
|
|
<parameter name="UART0_PinMuxing" value="Unused" />
|
|
<parameter name="UART1_Mode" value="No_flow_control" />
|
|
<parameter name="UART1_PinMuxing" value="IO" />
|
|
<parameter name="USB0_Mode" value="default" />
|
|
<parameter name="USB0_PinMuxing" value="IO" />
|
|
<parameter name="USB1_Mode" value="N/A" />
|
|
<parameter name="USB1_PinMuxing" value="Unused" />
|
|
<parameter name="USE_DEFAULT_MPU_CLK" value="false" />
|
|
<parameter name="device_name" value="10AS066N3F40I2SGES" />
|
|
<parameter name="eosc1_clk_mhz" value="25.0" />
|
|
<parameter name="quartus_ini_hps_ip_boot_from_fpga_ready" value="false" />
|
|
<parameter name="quartus_ini_hps_ip_enable_a10_advanced_options" value="false" />
|
|
<parameter name="quartus_ini_hps_ip_enable_emac_switch" value="false" />
|
|
<parameter name="quartus_ini_hps_ip_enable_jtag" value="false" />
|
|
<parameter name="quartus_ini_hps_ip_enable_sdmmc_clk_in" value="false" />
|
|
<parameter name="quartus_ini_hps_ip_enable_test_interface" value="false" />
|
|
<parameter name="quartus_ini_hps_ip_override_sdmmc_4bit" value="false" />
|
|
</module>
|
|
<module
|
|
name="emif_a10_hps_0"
|
|
kind="altera_emif_a10_hps"
|
|
version="15.1"
|
|
enabled="1">
|
|
<parameter name="BOARD_DDR3_AC_TO_CK_SKEW_NS" value="0.0" />
|
|
<parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
|
|
<parameter name="BOARD_DDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
|
|
<parameter name="BOARD_DDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
|
|
<parameter name="BOARD_DDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
|
|
<parameter name="BOARD_DDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
|
|
<parameter name="BOARD_DDR3_MAX_CK_DELAY_NS" value="0.6" />
|
|
<parameter name="BOARD_DDR3_MAX_DQS_DELAY_NS" value="0.6" />
|
|
<parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
|
|
<parameter name="BOARD_DDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
|
|
<parameter name="BOARD_DDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
|
|
<parameter name="BOARD_DDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
|
|
<parameter name="BOARD_DDR3_USER_AC_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_DDR3_USER_AC_SLEW_RATE" value="2.0" />
|
|
<parameter name="BOARD_DDR3_USER_CK_SLEW_RATE" value="4.0" />
|
|
<parameter name="BOARD_DDR3_USER_RCLK_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_DDR3_USER_RCLK_SLEW_RATE" value="5.0" />
|
|
<parameter name="BOARD_DDR3_USER_RDATA_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_DDR3_USER_RDATA_SLEW_RATE" value="2.5" />
|
|
<parameter name="BOARD_DDR3_USER_WCLK_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_DDR3_USER_WCLK_SLEW_RATE" value="4.0" />
|
|
<parameter name="BOARD_DDR3_USER_WDATA_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_DDR3_USER_WDATA_SLEW_RATE" value="2.0" />
|
|
<parameter name="BOARD_DDR3_USE_DEFAULT_ISI_VALUES" value="true" />
|
|
<parameter name="BOARD_DDR3_USE_DEFAULT_SLEW_RATES" value="true" />
|
|
<parameter name="BOARD_DDR4_AC_TO_CK_SKEW_NS" value="0.0" />
|
|
<parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
|
|
<parameter name="BOARD_DDR4_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
|
|
<parameter name="BOARD_DDR4_DQS_TO_CK_SKEW_NS" value="0.02" />
|
|
<parameter name="BOARD_DDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="false" />
|
|
<parameter name="BOARD_DDR4_IS_SKEW_WITHIN_DQS_DESKEWED" value="true" />
|
|
<parameter name="BOARD_DDR4_MAX_CK_DELAY_NS" value="0.6" />
|
|
<parameter name="BOARD_DDR4_MAX_DQS_DELAY_NS" value="0.6" />
|
|
<parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
|
|
<parameter name="BOARD_DDR4_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
|
|
<parameter name="BOARD_DDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
|
|
<parameter name="BOARD_DDR4_SKEW_BETWEEN_DQS_NS" value="0.02" />
|
|
<parameter name="BOARD_DDR4_USER_AC_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_DDR4_USER_AC_SLEW_RATE" value="2.0" />
|
|
<parameter name="BOARD_DDR4_USER_CK_SLEW_RATE" value="4.0" />
|
|
<parameter name="BOARD_DDR4_USER_RCLK_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_DDR4_USER_RCLK_SLEW_RATE" value="8.0" />
|
|
<parameter name="BOARD_DDR4_USER_RDATA_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_DDR4_USER_RDATA_SLEW_RATE" value="4.0" />
|
|
<parameter name="BOARD_DDR4_USER_WCLK_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_DDR4_USER_WCLK_SLEW_RATE" value="4.0" />
|
|
<parameter name="BOARD_DDR4_USER_WDATA_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_DDR4_USER_WDATA_SLEW_RATE" value="2.0" />
|
|
<parameter name="BOARD_DDR4_USE_DEFAULT_ISI_VALUES" value="true" />
|
|
<parameter name="BOARD_DDR4_USE_DEFAULT_SLEW_RATES" value="true" />
|
|
<parameter name="BOARD_LPDDR3_AC_TO_CK_SKEW_NS" value="0.0" />
|
|
<parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
|
|
<parameter name="BOARD_LPDDR3_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
|
|
<parameter name="BOARD_LPDDR3_DQS_TO_CK_SKEW_NS" value="0.02" />
|
|
<parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
|
|
<parameter name="BOARD_LPDDR3_IS_SKEW_WITHIN_DQS_DESKEWED" value="false" />
|
|
<parameter name="BOARD_LPDDR3_MAX_CK_DELAY_NS" value="0.6" />
|
|
<parameter name="BOARD_LPDDR3_MAX_DQS_DELAY_NS" value="0.6" />
|
|
<parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
|
|
<parameter name="BOARD_LPDDR3_PKG_BRD_SKEW_WITHIN_DQS_NS" value="0.02" />
|
|
<parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
|
|
<parameter name="BOARD_LPDDR3_SKEW_BETWEEN_DQS_NS" value="0.02" />
|
|
<parameter name="BOARD_LPDDR3_USER_AC_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_LPDDR3_USER_AC_SLEW_RATE" value="2.0" />
|
|
<parameter name="BOARD_LPDDR3_USER_CK_SLEW_RATE" value="4.0" />
|
|
<parameter name="BOARD_LPDDR3_USER_RCLK_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_LPDDR3_USER_RCLK_SLEW_RATE" value="4.0" />
|
|
<parameter name="BOARD_LPDDR3_USER_RDATA_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_LPDDR3_USER_RDATA_SLEW_RATE" value="2.0" />
|
|
<parameter name="BOARD_LPDDR3_USER_WCLK_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_LPDDR3_USER_WCLK_SLEW_RATE" value="4.0" />
|
|
<parameter name="BOARD_LPDDR3_USER_WDATA_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_LPDDR3_USER_WDATA_SLEW_RATE" value="2.0" />
|
|
<parameter name="BOARD_LPDDR3_USE_DEFAULT_ISI_VALUES" value="true" />
|
|
<parameter name="BOARD_LPDDR3_USE_DEFAULT_SLEW_RATES" value="true" />
|
|
<parameter name="BOARD_QDR2_AC_TO_K_SKEW_NS" value="0.0" />
|
|
<parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
|
|
<parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_D_NS" value="0.02" />
|
|
<parameter name="BOARD_QDR2_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
|
|
<parameter name="BOARD_QDR2_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
|
|
<parameter name="BOARD_QDR2_IS_SKEW_WITHIN_D_DESKEWED" value="false" />
|
|
<parameter name="BOARD_QDR2_IS_SKEW_WITHIN_Q_DESKEWED" value="false" />
|
|
<parameter name="BOARD_QDR2_MAX_K_DELAY_NS" value="0.6" />
|
|
<parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
|
|
<parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_D_NS" value="0.02" />
|
|
<parameter name="BOARD_QDR2_PKG_BRD_SKEW_WITHIN_Q_NS" value="0.02" />
|
|
<parameter name="BOARD_QDR2_USER_AC_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_QDR2_USER_AC_SLEW_RATE" value="2.0" />
|
|
<parameter name="BOARD_QDR2_USER_K_SLEW_RATE" value="4.0" />
|
|
<parameter name="BOARD_QDR2_USER_RCLK_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_QDR2_USER_RCLK_SLEW_RATE" value="4.0" />
|
|
<parameter name="BOARD_QDR2_USER_RDATA_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_QDR2_USER_RDATA_SLEW_RATE" value="2.0" />
|
|
<parameter name="BOARD_QDR2_USER_WCLK_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_QDR2_USER_WDATA_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_QDR2_USER_WDATA_SLEW_RATE" value="2.0" />
|
|
<parameter name="BOARD_QDR2_USE_DEFAULT_ISI_VALUES" value="true" />
|
|
<parameter name="BOARD_QDR2_USE_DEFAULT_SLEW_RATES" value="true" />
|
|
<parameter name="BOARD_QDR4_AC_TO_CK_SKEW_NS" value="0.0" />
|
|
<parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
|
|
<parameter name="BOARD_QDR4_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
|
|
<parameter name="BOARD_QDR4_DK_TO_CK_SKEW_NS" value="-0.02" />
|
|
<parameter name="BOARD_QDR4_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
|
|
<parameter name="BOARD_QDR4_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
|
|
<parameter name="BOARD_QDR4_MAX_CK_DELAY_NS" value="0.6" />
|
|
<parameter name="BOARD_QDR4_MAX_DK_DELAY_NS" value="0.6" />
|
|
<parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
|
|
<parameter name="BOARD_QDR4_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
|
|
<parameter name="BOARD_QDR4_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
|
|
<parameter name="BOARD_QDR4_SKEW_BETWEEN_DK_NS" value="0.02" />
|
|
<parameter name="BOARD_QDR4_USER_AC_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_QDR4_USER_AC_SLEW_RATE" value="2.0" />
|
|
<parameter name="BOARD_QDR4_USER_CK_SLEW_RATE" value="4.0" />
|
|
<parameter name="BOARD_QDR4_USER_RCLK_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_QDR4_USER_RCLK_SLEW_RATE" value="5.0" />
|
|
<parameter name="BOARD_QDR4_USER_RDATA_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_QDR4_USER_RDATA_SLEW_RATE" value="2.5" />
|
|
<parameter name="BOARD_QDR4_USER_WCLK_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_QDR4_USER_WCLK_SLEW_RATE" value="4.0" />
|
|
<parameter name="BOARD_QDR4_USER_WDATA_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_QDR4_USER_WDATA_SLEW_RATE" value="2.0" />
|
|
<parameter name="BOARD_QDR4_USE_DEFAULT_ISI_VALUES" value="true" />
|
|
<parameter name="BOARD_QDR4_USE_DEFAULT_SLEW_RATES" value="true" />
|
|
<parameter name="BOARD_RLD3_AC_TO_CK_SKEW_NS" value="0.0" />
|
|
<parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
|
|
<parameter name="BOARD_RLD3_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
|
|
<parameter name="BOARD_RLD3_DK_TO_CK_SKEW_NS" value="-0.02" />
|
|
<parameter name="BOARD_RLD3_IS_SKEW_WITHIN_AC_DESKEWED" value="true" />
|
|
<parameter name="BOARD_RLD3_IS_SKEW_WITHIN_QK_DESKEWED" value="false" />
|
|
<parameter name="BOARD_RLD3_MAX_CK_DELAY_NS" value="0.6" />
|
|
<parameter name="BOARD_RLD3_MAX_DK_DELAY_NS" value="0.6" />
|
|
<parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_AC_NS" value="0.02" />
|
|
<parameter name="BOARD_RLD3_PKG_BRD_SKEW_WITHIN_QK_NS" value="0.02" />
|
|
<parameter name="BOARD_RLD3_SKEW_BETWEEN_DIMMS_NS" value="0.05" />
|
|
<parameter name="BOARD_RLD3_SKEW_BETWEEN_DK_NS" value="0.02" />
|
|
<parameter name="BOARD_RLD3_USER_AC_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_RLD3_USER_AC_SLEW_RATE" value="2.0" />
|
|
<parameter name="BOARD_RLD3_USER_CK_SLEW_RATE" value="4.0" />
|
|
<parameter name="BOARD_RLD3_USER_RCLK_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_RLD3_USER_RCLK_SLEW_RATE" value="7.0" />
|
|
<parameter name="BOARD_RLD3_USER_RDATA_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_RLD3_USER_RDATA_SLEW_RATE" value="3.5" />
|
|
<parameter name="BOARD_RLD3_USER_WCLK_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_RLD3_USER_WCLK_SLEW_RATE" value="4.0" />
|
|
<parameter name="BOARD_RLD3_USER_WDATA_ISI_NS" value="0.0" />
|
|
<parameter name="BOARD_RLD3_USER_WDATA_SLEW_RATE" value="2.0" />
|
|
<parameter name="BOARD_RLD3_USE_DEFAULT_ISI_VALUES" value="true" />
|
|
<parameter name="BOARD_RLD3_USE_DEFAULT_SLEW_RATES" value="true" />
|
|
<parameter name="CAL_DEBUG_CLOCK_FREQUENCY" value="50000000" />
|
|
<parameter name="CTRL_DDR3_ADDR_ORDER_ENUM">DDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
|
|
<parameter name="CTRL_DDR3_AUTO_POWER_DOWN_CYCS" value="32" />
|
|
<parameter name="CTRL_DDR3_AUTO_POWER_DOWN_EN" value="false" />
|
|
<parameter name="CTRL_DDR3_AUTO_PRECHARGE_EN" value="false" />
|
|
<parameter name="CTRL_DDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_ST</parameter>
|
|
<parameter name="CTRL_DDR3_ECC_AUTO_CORRECTION_EN" value="false" />
|
|
<parameter name="CTRL_DDR3_ECC_EN" value="false" />
|
|
<parameter name="CTRL_DDR3_MMR_EN" value="false" />
|
|
<parameter name="CTRL_DDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
|
|
<parameter name="CTRL_DDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
|
|
<parameter name="CTRL_DDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
|
|
<parameter name="CTRL_DDR3_REORDER_EN" value="true" />
|
|
<parameter name="CTRL_DDR3_SELF_REFRESH_EN" value="false" />
|
|
<parameter name="CTRL_DDR3_STARVE_LIMIT" value="10" />
|
|
<parameter name="CTRL_DDR3_USER_PRIORITY_EN" value="false" />
|
|
<parameter name="CTRL_DDR3_USER_REFRESH_EN" value="false" />
|
|
<parameter name="CTRL_DDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
|
|
<parameter name="CTRL_DDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
|
|
<parameter name="CTRL_DDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
|
|
<parameter name="CTRL_DDR4_ADDR_ORDER_ENUM">DDR4_CTRL_ADDR_ORDER_CS_R_B_C_BG</parameter>
|
|
<parameter name="CTRL_DDR4_AUTO_POWER_DOWN_CYCS" value="32" />
|
|
<parameter name="CTRL_DDR4_AUTO_POWER_DOWN_EN" value="false" />
|
|
<parameter name="CTRL_DDR4_AUTO_PRECHARGE_EN" value="false" />
|
|
<parameter name="CTRL_DDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_ST</parameter>
|
|
<parameter name="CTRL_DDR4_ECC_AUTO_CORRECTION_EN" value="false" />
|
|
<parameter name="CTRL_DDR4_ECC_EN" value="false" />
|
|
<parameter name="CTRL_DDR4_MMR_EN" value="false" />
|
|
<parameter name="CTRL_DDR4_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
|
|
<parameter name="CTRL_DDR4_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
|
|
<parameter name="CTRL_DDR4_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
|
|
<parameter name="CTRL_DDR4_REORDER_EN" value="true" />
|
|
<parameter name="CTRL_DDR4_SELF_REFRESH_EN" value="false" />
|
|
<parameter name="CTRL_DDR4_STARVE_LIMIT" value="10" />
|
|
<parameter name="CTRL_DDR4_USER_PRIORITY_EN" value="false" />
|
|
<parameter name="CTRL_DDR4_USER_REFRESH_EN" value="false" />
|
|
<parameter name="CTRL_DDR4_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
|
|
<parameter name="CTRL_DDR4_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
|
|
<parameter name="CTRL_DDR4_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
|
|
<parameter name="CTRL_LPDDR3_ADDR_ORDER_ENUM">LPDDR3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
|
|
<parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_CYCS" value="32" />
|
|
<parameter name="CTRL_LPDDR3_AUTO_POWER_DOWN_EN" value="false" />
|
|
<parameter name="CTRL_LPDDR3_AUTO_PRECHARGE_EN" value="false" />
|
|
<parameter name="CTRL_LPDDR3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_ST</parameter>
|
|
<parameter name="CTRL_LPDDR3_MMR_EN" value="false" />
|
|
<parameter name="CTRL_LPDDR3_RD_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
|
|
<parameter name="CTRL_LPDDR3_RD_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
|
|
<parameter name="CTRL_LPDDR3_RD_TO_WR_SAME_CHIP_DELTA_CYCS" value="0" />
|
|
<parameter name="CTRL_LPDDR3_REORDER_EN" value="true" />
|
|
<parameter name="CTRL_LPDDR3_SELF_REFRESH_EN" value="false" />
|
|
<parameter name="CTRL_LPDDR3_STARVE_LIMIT" value="10" />
|
|
<parameter name="CTRL_LPDDR3_USER_PRIORITY_EN" value="false" />
|
|
<parameter name="CTRL_LPDDR3_USER_REFRESH_EN" value="false" />
|
|
<parameter name="CTRL_LPDDR3_WR_TO_RD_DIFF_CHIP_DELTA_CYCS" value="0" />
|
|
<parameter name="CTRL_LPDDR3_WR_TO_RD_SAME_CHIP_DELTA_CYCS" value="0" />
|
|
<parameter name="CTRL_LPDDR3_WR_TO_WR_DIFF_CHIP_DELTA_CYCS" value="0" />
|
|
<parameter name="CTRL_QDR2_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
|
|
<parameter name="CTRL_QDR2_AVL_MAX_BURST_COUNT" value="4" />
|
|
<parameter name="CTRL_QDR2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
|
|
<parameter name="CTRL_QDR4_ADD_RAW_TURNAROUND_DELAY_CYC" value="0" />
|
|
<parameter name="CTRL_QDR4_ADD_WAR_TURNAROUND_DELAY_CYC" value="0" />
|
|
<parameter name="CTRL_QDR4_AVL_ENABLE_POWER_OF_TWO_BUS" value="false" />
|
|
<parameter name="CTRL_QDR4_AVL_MAX_BURST_COUNT" value="4" />
|
|
<parameter name="CTRL_QDR4_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
|
|
<parameter name="CTRL_RLD2_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
|
|
<parameter name="CTRL_RLD3_ADDR_ORDER_ENUM">RLD3_CTRL_ADDR_ORDER_CS_R_B_C</parameter>
|
|
<parameter name="CTRL_RLD3_AVL_PROTOCOL_ENUM">CTRL_AVL_PROTOCOL_MM</parameter>
|
|
<parameter name="DIAG_BOARD_DELAY_CONFIG_STR" value="" />
|
|
<parameter name="DIAG_DDR3_ABSTRACT_PHY" value="false" />
|
|
<parameter name="DIAG_DDR3_BYPASS_DEFAULT_PATTERN" value="false" />
|
|
<parameter name="DIAG_DDR3_BYPASS_USER_STAGE" value="true" />
|
|
<parameter name="DIAG_DDR3_CAL_ADDR0" value="0" />
|
|
<parameter name="DIAG_DDR3_CAL_ADDR1" value="8" />
|
|
<parameter name="DIAG_DDR3_CAL_ENABLE_NON_DES" value="false" />
|
|
<parameter name="DIAG_DDR3_CAL_FULL_CAL_ON_RESET" value="true" />
|
|
<parameter name="DIAG_DDR3_CA_LEVEL_EN" value="false" />
|
|
<parameter name="DIAG_DDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
|
|
<parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
|
|
<parameter name="DIAG_DDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
|
|
<parameter name="DIAG_DDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
|
|
<parameter name="DIAG_DDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
|
|
<parameter name="DIAG_DDR3_INTERFACE_ID" value="0" />
|
|
<parameter name="DIAG_DDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
|
|
<parameter name="DIAG_DDR3_TG_BE_PATTERN_LENGTH" value="8" />
|
|
<parameter name="DIAG_DDR3_TG_DATA_PATTERN_LENGTH" value="8" />
|
|
<parameter name="DIAG_DDR3_USE_TG_AVL_2" value="false" />
|
|
<parameter name="DIAG_DDR4_ABSTRACT_PHY" value="false" />
|
|
<parameter name="DIAG_DDR4_BYPASS_DEFAULT_PATTERN" value="false" />
|
|
<parameter name="DIAG_DDR4_BYPASS_USER_STAGE" value="true" />
|
|
<parameter name="DIAG_DDR4_CAL_ADDR0" value="0" />
|
|
<parameter name="DIAG_DDR4_CAL_ADDR1" value="8" />
|
|
<parameter name="DIAG_DDR4_CAL_ENABLE_NON_DES" value="false" />
|
|
<parameter name="DIAG_DDR4_CAL_FULL_CAL_ON_RESET" value="true" />
|
|
<parameter name="DIAG_DDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
|
|
<parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_MASTER" value="false" />
|
|
<parameter name="DIAG_DDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
|
|
<parameter name="DIAG_DDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
|
|
<parameter name="DIAG_DDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
|
|
<parameter name="DIAG_DDR4_INTERFACE_ID" value="0" />
|
|
<parameter name="DIAG_DDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
|
|
<parameter name="DIAG_DDR4_SKIP_CA_DESKEW" value="false" />
|
|
<parameter name="DIAG_DDR4_SKIP_CA_LEVEL" value="true" />
|
|
<parameter name="DIAG_DDR4_SKIP_VREF_CAL" value="false" />
|
|
<parameter name="DIAG_DDR4_TG_BE_PATTERN_LENGTH" value="8" />
|
|
<parameter name="DIAG_DDR4_TG_DATA_PATTERN_LENGTH" value="8" />
|
|
<parameter name="DIAG_DDR4_USE_TG_AVL_2" value="false" />
|
|
<parameter name="DIAG_ECLIPSE_DEBUG" value="false" />
|
|
<parameter name="DIAG_ENABLE_HPS_EMIF_DEBUG" value="false" />
|
|
<parameter name="DIAG_ENABLE_JTAG_UART" value="false" />
|
|
<parameter name="DIAG_ENABLE_JTAG_UART_HEX" value="false" />
|
|
<parameter name="DIAG_EXPORT_VJI" value="false" />
|
|
<parameter name="DIAG_EXPOSE_DFT_SIGNALS" value="false" />
|
|
<parameter name="DIAG_EXTRA_CONFIGS" value="" />
|
|
<parameter name="DIAG_EX_DESIGN_ADD_TEST_EMIFS" value="" />
|
|
<parameter name="DIAG_FAST_SIM_OVERRIDE">FAST_SIM_OVERRIDE_DEFAULT</parameter>
|
|
<parameter name="DIAG_LPDDR3_ABSTRACT_PHY" value="false" />
|
|
<parameter name="DIAG_LPDDR3_BYPASS_DEFAULT_PATTERN" value="false" />
|
|
<parameter name="DIAG_LPDDR3_BYPASS_USER_STAGE" value="true" />
|
|
<parameter name="DIAG_LPDDR3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
|
|
<parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_MASTER" value="false" />
|
|
<parameter name="DIAG_LPDDR3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
|
|
<parameter name="DIAG_LPDDR3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
|
|
<parameter name="DIAG_LPDDR3_EX_DESIGN_SEPARATE_RZQS" value="false" />
|
|
<parameter name="DIAG_LPDDR3_INTERFACE_ID" value="0" />
|
|
<parameter name="DIAG_LPDDR3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
|
|
<parameter name="DIAG_LPDDR3_SKIP_CA_DESKEW" value="false" />
|
|
<parameter name="DIAG_LPDDR3_SKIP_CA_LEVEL" value="false" />
|
|
<parameter name="DIAG_LPDDR3_TG_BE_PATTERN_LENGTH" value="8" />
|
|
<parameter name="DIAG_LPDDR3_TG_DATA_PATTERN_LENGTH" value="8" />
|
|
<parameter name="DIAG_LPDDR3_USE_TG_AVL_2" value="false" />
|
|
<parameter name="DIAG_QDR2_ABSTRACT_PHY" value="false" />
|
|
<parameter name="DIAG_QDR2_BYPASS_DEFAULT_PATTERN" value="false" />
|
|
<parameter name="DIAG_QDR2_BYPASS_USER_STAGE" value="true" />
|
|
<parameter name="DIAG_QDR2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
|
|
<parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_MASTER" value="false" />
|
|
<parameter name="DIAG_QDR2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
|
|
<parameter name="DIAG_QDR2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
|
|
<parameter name="DIAG_QDR2_EX_DESIGN_SEPARATE_RZQS" value="false" />
|
|
<parameter name="DIAG_QDR2_INTERFACE_ID" value="0" />
|
|
<parameter name="DIAG_QDR2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
|
|
<parameter name="DIAG_QDR2_TG_BE_PATTERN_LENGTH" value="8" />
|
|
<parameter name="DIAG_QDR2_TG_DATA_PATTERN_LENGTH" value="8" />
|
|
<parameter name="DIAG_QDR2_USE_TG_AVL_2" value="false" />
|
|
<parameter name="DIAG_QDR4_ABSTRACT_PHY" value="false" />
|
|
<parameter name="DIAG_QDR4_BYPASS_DEFAULT_PATTERN" value="false" />
|
|
<parameter name="DIAG_QDR4_BYPASS_USER_STAGE" value="true" />
|
|
<parameter name="DIAG_QDR4_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
|
|
<parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_MASTER" value="false" />
|
|
<parameter name="DIAG_QDR4_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
|
|
<parameter name="DIAG_QDR4_EX_DESIGN_NUM_OF_SLAVES" value="1" />
|
|
<parameter name="DIAG_QDR4_EX_DESIGN_SEPARATE_RZQS" value="false" />
|
|
<parameter name="DIAG_QDR4_INTERFACE_ID" value="0" />
|
|
<parameter name="DIAG_QDR4_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
|
|
<parameter name="DIAG_QDR4_SKIP_VREF_CAL" value="false" />
|
|
<parameter name="DIAG_QDR4_TG_BE_PATTERN_LENGTH" value="8" />
|
|
<parameter name="DIAG_QDR4_TG_DATA_PATTERN_LENGTH" value="8" />
|
|
<parameter name="DIAG_QDR4_USE_TG_AVL_2" value="false" />
|
|
<parameter name="DIAG_RLD2_ABSTRACT_PHY" value="false" />
|
|
<parameter name="DIAG_RLD2_BYPASS_DEFAULT_PATTERN" value="false" />
|
|
<parameter name="DIAG_RLD2_BYPASS_USER_STAGE" value="true" />
|
|
<parameter name="DIAG_RLD2_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
|
|
<parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_MASTER" value="false" />
|
|
<parameter name="DIAG_RLD2_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
|
|
<parameter name="DIAG_RLD2_EX_DESIGN_NUM_OF_SLAVES" value="1" />
|
|
<parameter name="DIAG_RLD2_EX_DESIGN_SEPARATE_RZQS" value="false" />
|
|
<parameter name="DIAG_RLD2_INTERFACE_ID" value="0" />
|
|
<parameter name="DIAG_RLD2_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
|
|
<parameter name="DIAG_RLD2_TG_BE_PATTERN_LENGTH" value="8" />
|
|
<parameter name="DIAG_RLD2_TG_DATA_PATTERN_LENGTH" value="8" />
|
|
<parameter name="DIAG_RLD2_USE_TG_AVL_2" value="false" />
|
|
<parameter name="DIAG_RLD3_ABSTRACT_PHY" value="false" />
|
|
<parameter name="DIAG_RLD3_BYPASS_DEFAULT_PATTERN" value="false" />
|
|
<parameter name="DIAG_RLD3_BYPASS_USER_STAGE" value="true" />
|
|
<parameter name="DIAG_RLD3_EFFICIENCY_MONITOR">EFFMON_MODE_DISABLED</parameter>
|
|
<parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_MASTER" value="false" />
|
|
<parameter name="DIAG_RLD3_EXPORT_SEQ_AVALON_SLAVE">CAL_DEBUG_EXPORT_MODE_DISABLED</parameter>
|
|
<parameter name="DIAG_RLD3_EX_DESIGN_NUM_OF_SLAVES" value="1" />
|
|
<parameter name="DIAG_RLD3_EX_DESIGN_SEPARATE_RZQS" value="false" />
|
|
<parameter name="DIAG_RLD3_INTERFACE_ID" value="0" />
|
|
<parameter name="DIAG_RLD3_SIM_CAL_MODE_ENUM" value="SIM_CAL_MODE_SKIP" />
|
|
<parameter name="DIAG_RLD3_TG_BE_PATTERN_LENGTH" value="8" />
|
|
<parameter name="DIAG_RLD3_TG_DATA_PATTERN_LENGTH" value="8" />
|
|
<parameter name="DIAG_RLD3_USE_TG_AVL_2" value="false" />
|
|
<parameter name="DIAG_RS232_UART_BAUDRATE" value="57600" />
|
|
<parameter name="DIAG_SIM_REGTEST_MODE" value="false" />
|
|
<parameter name="DIAG_SOFT_NIOS_CLOCK_FREQUENCY" value="100" />
|
|
<parameter name="DIAG_SOFT_NIOS_MODE">SOFT_NIOS_MODE_DISABLED</parameter>
|
|
<parameter name="DIAG_SYNTH_FOR_SIM" value="false" />
|
|
<parameter name="DIAG_TG_AVL_2_NUM_CFG_INTERFACES" value="0" />
|
|
<parameter name="DIAG_TIMING_REGTEST_MODE" value="false" />
|
|
<parameter name="DIAG_USE_BOARD_DELAY_MODEL" value="false" />
|
|
<parameter name="DIAG_USE_RS232_UART" value="false" />
|
|
<parameter name="DIAG_VERBOSE_IOAUX" value="false" />
|
|
<parameter name="EX_DESIGN_GUI_DDR3_GEN_SIM" value="true" />
|
|
<parameter name="EX_DESIGN_GUI_DDR3_GEN_SYNTH" value="true" />
|
|
<parameter name="EX_DESIGN_GUI_DDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
|
|
<parameter name="EX_DESIGN_GUI_DDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
|
|
<parameter name="EX_DESIGN_GUI_DDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
|
|
<parameter name="EX_DESIGN_GUI_DDR3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
|
|
<parameter name="EX_DESIGN_GUI_DDR4_GEN_SIM" value="true" />
|
|
<parameter name="EX_DESIGN_GUI_DDR4_GEN_SYNTH" value="true" />
|
|
<parameter name="EX_DESIGN_GUI_DDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
|
|
<parameter name="EX_DESIGN_GUI_DDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
|
|
<parameter name="EX_DESIGN_GUI_DDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
|
|
<parameter name="EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
|
|
<parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SIM" value="true" />
|
|
<parameter name="EX_DESIGN_GUI_LPDDR3_GEN_SYNTH" value="true" />
|
|
<parameter name="EX_DESIGN_GUI_LPDDR3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
|
|
<parameter name="EX_DESIGN_GUI_LPDDR3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
|
|
<parameter name="EX_DESIGN_GUI_LPDDR3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
|
|
<parameter
|
|
name="EX_DESIGN_GUI_LPDDR3_TARGET_DEV_KIT"
|
|
value="TARGET_DEV_KIT_NONE" />
|
|
<parameter name="EX_DESIGN_GUI_QDR2_GEN_SIM" value="true" />
|
|
<parameter name="EX_DESIGN_GUI_QDR2_GEN_SYNTH" value="true" />
|
|
<parameter name="EX_DESIGN_GUI_QDR2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
|
|
<parameter name="EX_DESIGN_GUI_QDR2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
|
|
<parameter name="EX_DESIGN_GUI_QDR2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
|
|
<parameter name="EX_DESIGN_GUI_QDR2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
|
|
<parameter name="EX_DESIGN_GUI_QDR4_GEN_SIM" value="true" />
|
|
<parameter name="EX_DESIGN_GUI_QDR4_GEN_SYNTH" value="true" />
|
|
<parameter name="EX_DESIGN_GUI_QDR4_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
|
|
<parameter name="EX_DESIGN_GUI_QDR4_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
|
|
<parameter name="EX_DESIGN_GUI_QDR4_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
|
|
<parameter name="EX_DESIGN_GUI_QDR4_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
|
|
<parameter name="EX_DESIGN_GUI_RLD2_GEN_SIM" value="true" />
|
|
<parameter name="EX_DESIGN_GUI_RLD2_GEN_SYNTH" value="true" />
|
|
<parameter name="EX_DESIGN_GUI_RLD2_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
|
|
<parameter name="EX_DESIGN_GUI_RLD2_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
|
|
<parameter name="EX_DESIGN_GUI_RLD2_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
|
|
<parameter name="EX_DESIGN_GUI_RLD2_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
|
|
<parameter name="EX_DESIGN_GUI_RLD3_GEN_SIM" value="true" />
|
|
<parameter name="EX_DESIGN_GUI_RLD3_GEN_SYNTH" value="true" />
|
|
<parameter name="EX_DESIGN_GUI_RLD3_HDL_FORMAT" value="HDL_FORMAT_VERILOG" />
|
|
<parameter name="EX_DESIGN_GUI_RLD3_PREV_PRESET" value="TARGET_DEV_KIT_NONE" />
|
|
<parameter name="EX_DESIGN_GUI_RLD3_SEL_DESIGN">AVAIL_EX_DESIGNS_GEN_DESIGN</parameter>
|
|
<parameter name="EX_DESIGN_GUI_RLD3_TARGET_DEV_KIT" value="TARGET_DEV_KIT_NONE" />
|
|
<parameter name="INTERNAL_TESTING_MODE" value="false" />
|
|
<parameter name="IS_ED_SLAVE" value="false" />
|
|
<parameter name="MEM_DDR3_ALERT_N_DQS_GROUP" value="0" />
|
|
<parameter name="MEM_DDR3_ALERT_N_PLACEMENT_ENUM">DDR3_ALERT_N_PLACEMENT_AC_LANES</parameter>
|
|
<parameter name="MEM_DDR3_ASR_ENUM" value="DDR3_ASR_MANUAL" />
|
|
<parameter name="MEM_DDR3_ATCL_ENUM" value="DDR3_ATCL_DISABLED" />
|
|
<parameter name="MEM_DDR3_BANK_ADDR_WIDTH" value="3" />
|
|
<parameter name="MEM_DDR3_BL_ENUM" value="DDR3_BL_BL8" />
|
|
<parameter name="MEM_DDR3_BT_ENUM" value="DDR3_BT_SEQUENTIAL" />
|
|
<parameter name="MEM_DDR3_CKE_PER_DIMM" value="1" />
|
|
<parameter name="MEM_DDR3_CK_WIDTH" value="1" />
|
|
<parameter name="MEM_DDR3_COL_ADDR_WIDTH" value="10" />
|
|
<parameter name="MEM_DDR3_DISCRETE_CS_WIDTH" value="1" />
|
|
<parameter name="MEM_DDR3_DLL_EN" value="true" />
|
|
<parameter name="MEM_DDR3_DM_EN" value="true" />
|
|
<parameter name="MEM_DDR3_DQ_PER_DQS" value="8" />
|
|
<parameter name="MEM_DDR3_DQ_WIDTH" value="32" />
|
|
<parameter name="MEM_DDR3_DRV_STR_ENUM" value="DDR3_DRV_STR_RZQ_7" />
|
|
<parameter name="MEM_DDR3_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
|
|
<parameter name="MEM_DDR3_LRDIMM_EXTENDED_CONFIG" value="000000000000000000" />
|
|
<parameter name="MEM_DDR3_MIRROR_ADDRESSING_EN" value="true" />
|
|
<parameter name="MEM_DDR3_NUM_OF_DIMMS" value="1" />
|
|
<parameter name="MEM_DDR3_PD_ENUM" value="DDR3_PD_OFF" />
|
|
<parameter name="MEM_DDR3_RANKS_PER_DIMM" value="1" />
|
|
<parameter name="MEM_DDR3_RDIMM_CONFIG" value="0000000000000000" />
|
|
<parameter name="MEM_DDR3_ROW_ADDR_WIDTH" value="15" />
|
|
<parameter name="MEM_DDR3_RTT_NOM_ENUM">DDR3_RTT_NOM_ODT_DISABLED</parameter>
|
|
<parameter name="MEM_DDR3_RTT_WR_ENUM" value="DDR3_RTT_WR_RZQ_4" />
|
|
<parameter name="MEM_DDR3_R_ODT0_1X1" value="off" />
|
|
<parameter name="MEM_DDR3_R_ODT0_2X2" value="off,off" />
|
|
<parameter name="MEM_DDR3_R_ODT0_4X2" value="off,off,on,on" />
|
|
<parameter name="MEM_DDR3_R_ODT0_4X4" value="off,off,off,off" />
|
|
<parameter name="MEM_DDR3_R_ODT1_2X2" value="off,off" />
|
|
<parameter name="MEM_DDR3_R_ODT1_4X2" value="on,on,off,off" />
|
|
<parameter name="MEM_DDR3_R_ODT1_4X4" value="off,off,on,on" />
|
|
<parameter name="MEM_DDR3_R_ODT2_4X4" value="off,off,off,off" />
|
|
<parameter name="MEM_DDR3_R_ODT3_4X4" value="on,on,off,off" />
|
|
<parameter name="MEM_DDR3_R_ODTN_1X1" value="Rank 0" />
|
|
<parameter name="MEM_DDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
|
|
<parameter name="MEM_DDR3_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
|
|
<parameter name="MEM_DDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
|
|
<parameter name="MEM_DDR3_SPEEDBIN_ENUM" value="DDR3_SPEEDBIN_2133" />
|
|
<parameter name="MEM_DDR3_SRT_ENUM" value="DDR3_SRT_NORMAL" />
|
|
<parameter name="MEM_DDR3_TCL" value="14" />
|
|
<parameter name="MEM_DDR3_TDH_DC_MV" value="100" />
|
|
<parameter name="MEM_DDR3_TDH_PS" value="55" />
|
|
<parameter name="MEM_DDR3_TDQSCK_PS" value="180" />
|
|
<parameter name="MEM_DDR3_TDQSQ_PS" value="75" />
|
|
<parameter name="MEM_DDR3_TDQSS_CYC" value="0.27" />
|
|
<parameter name="MEM_DDR3_TDSH_CYC" value="0.18" />
|
|
<parameter name="MEM_DDR3_TDSS_CYC" value="0.18" />
|
|
<parameter name="MEM_DDR3_TDS_AC_MV" value="135" />
|
|
<parameter name="MEM_DDR3_TDS_PS" value="53" />
|
|
<parameter name="MEM_DDR3_TFAW_NS" value="25.0" />
|
|
<parameter name="MEM_DDR3_TIH_DC_MV" value="100" />
|
|
<parameter name="MEM_DDR3_TIH_PS" value="95" />
|
|
<parameter name="MEM_DDR3_TINIT_US" value="500" />
|
|
<parameter name="MEM_DDR3_TIS_AC_MV" value="135" />
|
|
<parameter name="MEM_DDR3_TIS_PS" value="60" />
|
|
<parameter name="MEM_DDR3_TMRD_CK_CYC" value="4" />
|
|
<parameter name="MEM_DDR3_TQH_CYC" value="0.38" />
|
|
<parameter name="MEM_DDR3_TQSH_CYC" value="0.4" />
|
|
<parameter name="MEM_DDR3_TRAS_NS" value="33.0" />
|
|
<parameter name="MEM_DDR3_TRCD_NS" value="13.09" />
|
|
<parameter name="MEM_DDR3_TREFI_US" value="7.8" />
|
|
<parameter name="MEM_DDR3_TRFC_NS" value="160.0" />
|
|
<parameter name="MEM_DDR3_TRP_NS" value="13.09" />
|
|
<parameter name="MEM_DDR3_TRRD_CYC" value="6" />
|
|
<parameter name="MEM_DDR3_TRTP_CYC" value="8" />
|
|
<parameter name="MEM_DDR3_TWLH_PS" value="125.0" />
|
|
<parameter name="MEM_DDR3_TWLS_PS" value="125.0" />
|
|
<parameter name="MEM_DDR3_TWR_NS" value="15.0" />
|
|
<parameter name="MEM_DDR3_TWTR_CYC" value="8" />
|
|
<parameter name="MEM_DDR3_USE_DEFAULT_ODT" value="true" />
|
|
<parameter name="MEM_DDR3_WTCL" value="10" />
|
|
<parameter name="MEM_DDR3_W_ODT0_1X1" value="on" />
|
|
<parameter name="MEM_DDR3_W_ODT0_2X2" value="on,off" />
|
|
<parameter name="MEM_DDR3_W_ODT0_4X2" value="off,off,on,on" />
|
|
<parameter name="MEM_DDR3_W_ODT0_4X4" value="on,on,off,off" />
|
|
<parameter name="MEM_DDR3_W_ODT1_2X2" value="off,on" />
|
|
<parameter name="MEM_DDR3_W_ODT1_4X2" value="on,on,off,off" />
|
|
<parameter name="MEM_DDR3_W_ODT1_4X4" value="off,off,on,on" />
|
|
<parameter name="MEM_DDR3_W_ODT2_4X4" value="off,off,on,on" />
|
|
<parameter name="MEM_DDR3_W_ODT3_4X4" value="on,on,off,off" />
|
|
<parameter name="MEM_DDR3_W_ODTN_1X1" value="Rank 0" />
|
|
<parameter name="MEM_DDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
|
|
<parameter name="MEM_DDR3_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
|
|
<parameter name="MEM_DDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
|
|
<parameter name="MEM_DDR4_AC_PARITY_LATENCY">DDR4_AC_PARITY_LATENCY_DISABLE</parameter>
|
|
<parameter name="MEM_DDR4_AC_PERSISTENT_ERROR" value="false" />
|
|
<parameter name="MEM_DDR4_ALERT_N_AC_LANE" value="0" />
|
|
<parameter name="MEM_DDR4_ALERT_N_AC_PIN" value="0" />
|
|
<parameter name="MEM_DDR4_ALERT_N_DQS_GROUP" value="3" />
|
|
<parameter name="MEM_DDR4_ALERT_N_PLACEMENT_ENUM">DDR4_ALERT_N_PLACEMENT_DATA_LANES</parameter>
|
|
<parameter name="MEM_DDR4_ALERT_PAR_EN" value="true" />
|
|
<parameter name="MEM_DDR4_ASR_ENUM">DDR4_ASR_MANUAL_NORMAL</parameter>
|
|
<parameter name="MEM_DDR4_ATCL_ENUM" value="DDR4_ATCL_DISABLED" />
|
|
<parameter name="MEM_DDR4_BANK_ADDR_WIDTH" value="2" />
|
|
<parameter name="MEM_DDR4_BANK_GROUP_WIDTH" value="1" />
|
|
<parameter name="MEM_DDR4_BL_ENUM" value="DDR4_BL_BL8" />
|
|
<parameter name="MEM_DDR4_BT_ENUM" value="DDR4_BT_SEQUENTIAL" />
|
|
<parameter name="MEM_DDR4_CAL_MODE" value="0" />
|
|
<parameter name="MEM_DDR4_CHIP_ID_WIDTH" value="0" />
|
|
<parameter name="MEM_DDR4_CKE_PER_DIMM" value="1" />
|
|
<parameter name="MEM_DDR4_CK_WIDTH" value="1" />
|
|
<parameter name="MEM_DDR4_COL_ADDR_WIDTH" value="10" />
|
|
<parameter name="MEM_DDR4_DEFAULT_VREFOUT" value="true" />
|
|
<parameter name="MEM_DDR4_DISCRETE_CS_WIDTH" value="1" />
|
|
<parameter name="MEM_DDR4_DLL_EN" value="true" />
|
|
<parameter name="MEM_DDR4_DM_EN" value="true" />
|
|
<parameter name="MEM_DDR4_DQ_PER_DQS" value="8" />
|
|
<parameter name="MEM_DDR4_DQ_WIDTH" value="32" />
|
|
<parameter name="MEM_DDR4_DRV_STR_ENUM" value="DDR4_DRV_STR_RZQ_7" />
|
|
<parameter name="MEM_DDR4_FINE_GRANULARITY_REFRESH">DDR4_FINE_REFRESH_FIXED_1X</parameter>
|
|
<parameter name="MEM_DDR4_FORMAT_ENUM" value="MEM_FORMAT_UDIMM" />
|
|
<parameter name="MEM_DDR4_GEARDOWN" value="DDR4_GEARDOWN_HR" />
|
|
<parameter name="MEM_DDR4_INTERNAL_VREFDQ_MONITOR" value="false" />
|
|
<parameter name="MEM_DDR4_LRDIMM_EXTENDED_CONFIG" value="0000000000000000" />
|
|
<parameter name="MEM_DDR4_LRDIMM_VREFDQ_VALUE" value="1D" />
|
|
<parameter name="MEM_DDR4_MAX_POWERDOWN" value="false" />
|
|
<parameter name="MEM_DDR4_MIRROR_ADDRESSING_EN" value="true" />
|
|
<parameter name="MEM_DDR4_MPR_READ_FORMAT">DDR4_MPR_READ_FORMAT_SERIAL</parameter>
|
|
<parameter name="MEM_DDR4_NUM_OF_DIMMS" value="1" />
|
|
<parameter name="MEM_DDR4_ODT_IN_POWERDOWN" value="true" />
|
|
<parameter name="MEM_DDR4_PER_DRAM_ADDR" value="false" />
|
|
<parameter name="MEM_DDR4_RANKS_PER_DIMM" value="1" />
|
|
<parameter name="MEM_DDR4_RDIMM_CONFIG">00000000000000000000000000000000000000</parameter>
|
|
<parameter name="MEM_DDR4_READ_DBI" value="true" />
|
|
<parameter name="MEM_DDR4_READ_PREAMBLE" value="2" />
|
|
<parameter name="MEM_DDR4_READ_PREAMBLE_TRAINING" value="false" />
|
|
<parameter name="MEM_DDR4_ROW_ADDR_WIDTH" value="15" />
|
|
<parameter name="MEM_DDR4_RTT_NOM_ENUM" value="DDR4_RTT_NOM_RZQ_6" />
|
|
<parameter name="MEM_DDR4_RTT_PARK">DDR4_RTT_PARK_ODT_DISABLED</parameter>
|
|
<parameter name="MEM_DDR4_RTT_WR_ENUM">DDR4_RTT_WR_ODT_DISABLED</parameter>
|
|
<parameter name="MEM_DDR4_R_ODT0_1X1" value="off" />
|
|
<parameter name="MEM_DDR4_R_ODT0_2X2" value="off,off" />
|
|
<parameter name="MEM_DDR4_R_ODT0_4X2" value="off,off,on,on" />
|
|
<parameter name="MEM_DDR4_R_ODT0_4X4" value="off,off,off,off" />
|
|
<parameter name="MEM_DDR4_R_ODT1_2X2" value="off,off" />
|
|
<parameter name="MEM_DDR4_R_ODT1_4X2" value="on,on,off,off" />
|
|
<parameter name="MEM_DDR4_R_ODT1_4X4" value="off,off,on,on" />
|
|
<parameter name="MEM_DDR4_R_ODT2_4X4" value="off,off,off,off" />
|
|
<parameter name="MEM_DDR4_R_ODT3_4X4" value="on,on,off,off" />
|
|
<parameter name="MEM_DDR4_R_ODTN_1X1" value="Rank 0" />
|
|
<parameter name="MEM_DDR4_R_ODTN_2X2" value="Rank 0,Rank 1" />
|
|
<parameter name="MEM_DDR4_R_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
|
|
<parameter name="MEM_DDR4_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
|
|
<parameter name="MEM_DDR4_SELF_RFSH_ABORT" value="false" />
|
|
<parameter name="MEM_DDR4_SPEEDBIN_ENUM" value="DDR4_SPEEDBIN_2666" />
|
|
<parameter name="MEM_DDR4_TCCD_L_CYC" value="6" />
|
|
<parameter name="MEM_DDR4_TCCD_S_CYC" value="4" />
|
|
<parameter name="MEM_DDR4_TCL" value="20" />
|
|
<parameter name="MEM_DDR4_TDIVW_DJ_CYC" value="0.1" />
|
|
<parameter name="MEM_DDR4_TDIVW_TOTAL_UI" value="0.2" />
|
|
<parameter name="MEM_DDR4_TDQSCK_PS" value="165" />
|
|
<parameter name="MEM_DDR4_TDQSQ_PS" value="66" />
|
|
<parameter name="MEM_DDR4_TDQSQ_UI" value="0.16" />
|
|
<parameter name="MEM_DDR4_TDQSS_CYC" value="0.27" />
|
|
<parameter name="MEM_DDR4_TDSH_CYC" value="0.18" />
|
|
<parameter name="MEM_DDR4_TDSS_CYC" value="0.18" />
|
|
<parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_ENA" value="false" />
|
|
<parameter name="MEM_DDR4_TEMP_CONTROLLED_RFSH_RANGE">DDR4_TEMP_CONTROLLED_RFSH_NORMAL</parameter>
|
|
<parameter name="MEM_DDR4_TEMP_SENSOR_READOUT" value="false" />
|
|
<parameter name="MEM_DDR4_TFAW_NS" value="30.0" />
|
|
<parameter name="MEM_DDR4_TIH_DC_MV" value="75" />
|
|
<parameter name="MEM_DDR4_TIH_PS" value="95" />
|
|
<parameter name="MEM_DDR4_TINIT_US" value="500" />
|
|
<parameter name="MEM_DDR4_TIS_AC_MV" value="100" />
|
|
<parameter name="MEM_DDR4_TIS_PS" value="60" />
|
|
<parameter name="MEM_DDR4_TMRD_CK_CYC" value="8" />
|
|
<parameter name="MEM_DDR4_TQH_CYC" value="0.38" />
|
|
<parameter name="MEM_DDR4_TQH_UI" value="0.76" />
|
|
<parameter name="MEM_DDR4_TQSH_CYC" value="0.38" />
|
|
<parameter name="MEM_DDR4_TRAS_NS" value="32.0" />
|
|
<parameter name="MEM_DDR4_TRCD_NS" value="14.25" />
|
|
<parameter name="MEM_DDR4_TREFI_US" value="7.8" />
|
|
<parameter name="MEM_DDR4_TRFC_NS" value="260.0" />
|
|
<parameter name="MEM_DDR4_TRP_NS" value="14.25" />
|
|
<parameter name="MEM_DDR4_TRRD_L_CYC" value="8" />
|
|
<parameter name="MEM_DDR4_TRRD_S_CYC" value="7" />
|
|
<parameter name="MEM_DDR4_TWLH_PS" value="108.0" />
|
|
<parameter name="MEM_DDR4_TWLS_PS" value="108.0" />
|
|
<parameter name="MEM_DDR4_TWR_NS" value="15.0" />
|
|
<parameter name="MEM_DDR4_TWTR_L_CYC" value="10" />
|
|
<parameter name="MEM_DDR4_TWTR_S_CYC" value="4" />
|
|
<parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_RANGE">DDR4_VREFDQ_TRAINING_RANGE_1</parameter>
|
|
<parameter name="MEM_DDR4_USER_VREFDQ_TRAINING_VALUE" value="56.0" />
|
|
<parameter name="MEM_DDR4_USE_DEFAULT_ODT" value="true" />
|
|
<parameter name="MEM_DDR4_VDIVW_TOTAL" value="136" />
|
|
<parameter name="MEM_DDR4_WRITE_CRC" value="false" />
|
|
<parameter name="MEM_DDR4_WRITE_DBI" value="false" />
|
|
<parameter name="MEM_DDR4_WRITE_PREAMBLE" value="1" />
|
|
<parameter name="MEM_DDR4_WTCL" value="18" />
|
|
<parameter name="MEM_DDR4_W_ODT0_1X1" value="on" />
|
|
<parameter name="MEM_DDR4_W_ODT0_2X2" value="on,off" />
|
|
<parameter name="MEM_DDR4_W_ODT0_4X2" value="off,off,on,on" />
|
|
<parameter name="MEM_DDR4_W_ODT0_4X4" value="on,on,off,off" />
|
|
<parameter name="MEM_DDR4_W_ODT1_2X2" value="off,on" />
|
|
<parameter name="MEM_DDR4_W_ODT1_4X2" value="on,on,off,off" />
|
|
<parameter name="MEM_DDR4_W_ODT1_4X4" value="off,off,on,on" />
|
|
<parameter name="MEM_DDR4_W_ODT2_4X4" value="off,off,on,on" />
|
|
<parameter name="MEM_DDR4_W_ODT3_4X4" value="on,on,off,off" />
|
|
<parameter name="MEM_DDR4_W_ODTN_1X1" value="Rank 0" />
|
|
<parameter name="MEM_DDR4_W_ODTN_2X2" value="Rank 0,Rank 1" />
|
|
<parameter name="MEM_DDR4_W_ODTN_4X2">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
|
|
<parameter name="MEM_DDR4_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
|
|
<parameter name="MEM_LPDDR3_BANK_ADDR_WIDTH" value="3" />
|
|
<parameter name="MEM_LPDDR3_BL" value="LPDDR3_BL_BL8" />
|
|
<parameter name="MEM_LPDDR3_COL_ADDR_WIDTH" value="10" />
|
|
<parameter name="MEM_LPDDR3_DATA_LATENCY" value="LPDDR3_DL_RL12_WL6" />
|
|
<parameter name="MEM_LPDDR3_DISCRETE_CS_WIDTH" value="1" />
|
|
<parameter name="MEM_LPDDR3_DM_EN" value="true" />
|
|
<parameter name="MEM_LPDDR3_DQODT">LPDDR3_DQODT_DISABLE</parameter>
|
|
<parameter name="MEM_LPDDR3_DQ_WIDTH" value="32" />
|
|
<parameter name="MEM_LPDDR3_DRV_STR">LPDDR3_DRV_STR_40D_40U</parameter>
|
|
<parameter name="MEM_LPDDR3_NWR" value="LPDDR3_NWR_NWR10" />
|
|
<parameter name="MEM_LPDDR3_PDODT">LPDDR3_PDODT_DISABLED</parameter>
|
|
<parameter name="MEM_LPDDR3_ROW_ADDR_WIDTH" value="15" />
|
|
<parameter name="MEM_LPDDR3_R_ODT0_1X1" value="off" />
|
|
<parameter name="MEM_LPDDR3_R_ODT0_2X2" value="off,off" />
|
|
<parameter name="MEM_LPDDR3_R_ODT0_4X4" value="off,off,on,on" />
|
|
<parameter name="MEM_LPDDR3_R_ODT1_2X2" value="off,off" />
|
|
<parameter name="MEM_LPDDR3_R_ODT1_4X4" value="off,off,off,off" />
|
|
<parameter name="MEM_LPDDR3_R_ODT2_4X4" value="on,on,off,off" />
|
|
<parameter name="MEM_LPDDR3_R_ODT3_4X4" value="off,off,off,off" />
|
|
<parameter name="MEM_LPDDR3_R_ODTN_1X1" value="Rank 0" />
|
|
<parameter name="MEM_LPDDR3_R_ODTN_2X2" value="Rank 0,Rank 1" />
|
|
<parameter name="MEM_LPDDR3_R_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
|
|
<parameter name="MEM_LPDDR3_SPEEDBIN_ENUM">LPDDR3_SPEEDBIN_1600</parameter>
|
|
<parameter name="MEM_LPDDR3_TDH_DC_MV" value="100" />
|
|
<parameter name="MEM_LPDDR3_TDH_PS" value="100" />
|
|
<parameter name="MEM_LPDDR3_TDQSCK_PS" value="614" />
|
|
<parameter name="MEM_LPDDR3_TDQSQ_PS" value="135" />
|
|
<parameter name="MEM_LPDDR3_TDQSS_CYC" value="1.25" />
|
|
<parameter name="MEM_LPDDR3_TDSH_CYC" value="0.2" />
|
|
<parameter name="MEM_LPDDR3_TDSS_CYC" value="0.2" />
|
|
<parameter name="MEM_LPDDR3_TDS_AC_MV" value="150" />
|
|
<parameter name="MEM_LPDDR3_TDS_PS" value="75" />
|
|
<parameter name="MEM_LPDDR3_TFAW_NS" value="50.0" />
|
|
<parameter name="MEM_LPDDR3_TIH_DC_MV" value="100" />
|
|
<parameter name="MEM_LPDDR3_TIH_PS" value="100" />
|
|
<parameter name="MEM_LPDDR3_TINIT_US" value="500" />
|
|
<parameter name="MEM_LPDDR3_TIS_AC_MV" value="150" />
|
|
<parameter name="MEM_LPDDR3_TIS_PS" value="75" />
|
|
<parameter name="MEM_LPDDR3_TMRR_CK_CYC" value="4" />
|
|
<parameter name="MEM_LPDDR3_TMRW_CK_CYC" value="10" />
|
|
<parameter name="MEM_LPDDR3_TQH_CYC" value="0.38" />
|
|
<parameter name="MEM_LPDDR3_TQSH_CYC" value="0.38" />
|
|
<parameter name="MEM_LPDDR3_TRAS_NS" value="42.5" />
|
|
<parameter name="MEM_LPDDR3_TRCD_NS" value="18.75" />
|
|
<parameter name="MEM_LPDDR3_TREFI_US" value="3.9" />
|
|
<parameter name="MEM_LPDDR3_TRFC_NS" value="210.0" />
|
|
<parameter name="MEM_LPDDR3_TRP_NS" value="18.75" />
|
|
<parameter name="MEM_LPDDR3_TRRD_CYC" value="2" />
|
|
<parameter name="MEM_LPDDR3_TRTP_CYC" value="4" />
|
|
<parameter name="MEM_LPDDR3_TWLH_PS" value="175.0" />
|
|
<parameter name="MEM_LPDDR3_TWLS_PS" value="175.0" />
|
|
<parameter name="MEM_LPDDR3_TWR_NS" value="15.0" />
|
|
<parameter name="MEM_LPDDR3_TWTR_CYC" value="4" />
|
|
<parameter name="MEM_LPDDR3_USE_DEFAULT_ODT" value="true" />
|
|
<parameter name="MEM_LPDDR3_W_ODT0_1X1" value="on" />
|
|
<parameter name="MEM_LPDDR3_W_ODT0_2X2" value="on,off" />
|
|
<parameter name="MEM_LPDDR3_W_ODT0_4X4" value="on,on,on,on" />
|
|
<parameter name="MEM_LPDDR3_W_ODT1_2X2" value="off,on" />
|
|
<parameter name="MEM_LPDDR3_W_ODT1_4X4" value="off,off,off,off" />
|
|
<parameter name="MEM_LPDDR3_W_ODT2_4X4" value="on,on,on,on" />
|
|
<parameter name="MEM_LPDDR3_W_ODT3_4X4" value="off,off,off,off" />
|
|
<parameter name="MEM_LPDDR3_W_ODTN_1X1" value="Rank 0" />
|
|
<parameter name="MEM_LPDDR3_W_ODTN_2X2" value="Rank 0,Rank 1" />
|
|
<parameter name="MEM_LPDDR3_W_ODTN_4X4">Rank 0,Rank 1,Rank 2,Rank 3</parameter>
|
|
<parameter name="MEM_QDR2_ADDR_WIDTH" value="19" />
|
|
<parameter name="MEM_QDR2_BL" value="4" />
|
|
<parameter name="MEM_QDR2_BWS_EN" value="true" />
|
|
<parameter name="MEM_QDR2_DATA_PER_DEVICE" value="36" />
|
|
<parameter name="MEM_QDR2_INTERNAL_JITTER_NS" value="0.08" />
|
|
<parameter name="MEM_QDR2_SPEEDBIN_ENUM" value="QDR2_SPEEDBIN_633" />
|
|
<parameter name="MEM_QDR2_TCCQO_NS" value="0.45" />
|
|
<parameter name="MEM_QDR2_TCQDOH_NS" value="-0.09" />
|
|
<parameter name="MEM_QDR2_TCQD_NS" value="0.09" />
|
|
<parameter name="MEM_QDR2_TCQH_NS" value="0.71" />
|
|
<parameter name="MEM_QDR2_THA_NS" value="0.18" />
|
|
<parameter name="MEM_QDR2_THD_NS" value="0.18" />
|
|
<parameter name="MEM_QDR2_TRL_CYC" value="2.5" />
|
|
<parameter name="MEM_QDR2_TSA_NS" value="0.23" />
|
|
<parameter name="MEM_QDR2_TSD_NS" value="0.23" />
|
|
<parameter name="MEM_QDR2_WIDTH_EXPANDED" value="false" />
|
|
<parameter name="MEM_QDR4_AC_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
|
|
<parameter name="MEM_QDR4_ADDR_INV_ENA" value="false" />
|
|
<parameter name="MEM_QDR4_ADDR_WIDTH" value="21" />
|
|
<parameter name="MEM_QDR4_CK_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
|
|
<parameter name="MEM_QDR4_DATA_INV_ENA" value="false" />
|
|
<parameter name="MEM_QDR4_DATA_ODT_MODE_ENUM" value="QDR4_ODT_25_PCT" />
|
|
<parameter name="MEM_QDR4_DQ_PER_PORT_PER_DEVICE" value="36" />
|
|
<parameter name="MEM_QDR4_PD_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
|
|
<parameter name="MEM_QDR4_PU_OUTPUT_DRIVE_MODE_ENUM">QDR4_OUTPUT_DRIVE_25_PCT</parameter>
|
|
<parameter name="MEM_QDR4_SPEEDBIN_ENUM" value="QDR4_SPEEDBIN_2133" />
|
|
<parameter name="MEM_QDR4_TAH_PS" value="125" />
|
|
<parameter name="MEM_QDR4_TAS_PS" value="125" />
|
|
<parameter name="MEM_QDR4_TCH_PS" value="150" />
|
|
<parameter name="MEM_QDR4_TCKDK_MAX_PS" value="150" />
|
|
<parameter name="MEM_QDR4_TCKDK_MIN_PS" value="-150" />
|
|
<parameter name="MEM_QDR4_TCKQK_MAX_PS" value="225" />
|
|
<parameter name="MEM_QDR4_TCS_PS" value="150" />
|
|
<parameter name="MEM_QDR4_TIH_PS" value="125" />
|
|
<parameter name="MEM_QDR4_TIS_PS" value="125" />
|
|
<parameter name="MEM_QDR4_TQH_CYC" value="0.4" />
|
|
<parameter name="MEM_QDR4_TQKQ_MAX_PS" value="75" />
|
|
<parameter name="MEM_QDR4_WIDTH_EXPANDED" value="false" />
|
|
<parameter name="MEM_RLD2_ADDR_WIDTH" value="21" />
|
|
<parameter name="MEM_RLD2_BANK_ADDR_WIDTH" value="3" />
|
|
<parameter name="MEM_RLD2_BL" value="4" />
|
|
<parameter name="MEM_RLD2_CONFIG_ENUM">RLD2_CONFIG_TRC_8_TRL_8_TWL_9</parameter>
|
|
<parameter name="MEM_RLD2_DM_EN" value="true" />
|
|
<parameter name="MEM_RLD2_DQ_PER_DEVICE" value="9" />
|
|
<parameter name="MEM_RLD2_DRIVE_IMPEDENCE_ENUM">RLD2_DRIVE_IMPEDENCE_INTERNAL_50</parameter>
|
|
<parameter name="MEM_RLD2_ODT_MODE_ENUM" value="RLD2_ODT_ON" />
|
|
<parameter name="MEM_RLD2_REFRESH_INTERVAL_US" value="0.24" />
|
|
<parameter name="MEM_RLD2_SPEEDBIN_ENUM" value="RLD2_SPEEDBIN_18" />
|
|
<parameter name="MEM_RLD2_TAH_NS" value="0.3" />
|
|
<parameter name="MEM_RLD2_TAS_NS" value="0.3" />
|
|
<parameter name="MEM_RLD2_TCKDK_MAX_NS" value="0.3" />
|
|
<parameter name="MEM_RLD2_TCKDK_MIN_NS" value="-0.3" />
|
|
<parameter name="MEM_RLD2_TCKH_CYC" value="0.45" />
|
|
<parameter name="MEM_RLD2_TCKQK_MAX_NS" value="0.2" />
|
|
<parameter name="MEM_RLD2_TDH_NS" value="0.17" />
|
|
<parameter name="MEM_RLD2_TDS_NS" value="0.17" />
|
|
<parameter name="MEM_RLD2_TQKH_HCYC" value="0.9" />
|
|
<parameter name="MEM_RLD2_TQKQ_MAX_NS" value="0.12" />
|
|
<parameter name="MEM_RLD2_TQKQ_MIN_NS" value="-0.12" />
|
|
<parameter name="MEM_RLD2_WIDTH_EXPANDED" value="false" />
|
|
<parameter name="MEM_RLD3_ADDR_WIDTH" value="20" />
|
|
<parameter name="MEM_RLD3_AREF_PROTOCOL_ENUM" value="RLD3_AREF_BAC" />
|
|
<parameter name="MEM_RLD3_BANK_ADDR_WIDTH" value="4" />
|
|
<parameter name="MEM_RLD3_BL" value="2" />
|
|
<parameter name="MEM_RLD3_DATA_LATENCY_MODE_ENUM" value="RLD3_DL_RL16_WL17" />
|
|
<parameter name="MEM_RLD3_DEPTH_EXPANDED" value="false" />
|
|
<parameter name="MEM_RLD3_DM_EN" value="true" />
|
|
<parameter name="MEM_RLD3_DQ_PER_DEVICE" value="36" />
|
|
<parameter name="MEM_RLD3_ODT_MODE_ENUM" value="RLD3_ODT_40" />
|
|
<parameter name="MEM_RLD3_OUTPUT_DRIVE_MODE_ENUM">RLD3_OUTPUT_DRIVE_40</parameter>
|
|
<parameter name="MEM_RLD3_SPEEDBIN_ENUM" value="RLD3_SPEEDBIN_093E" />
|
|
<parameter name="MEM_RLD3_TCKDK_MAX_CYC" value="0.27" />
|
|
<parameter name="MEM_RLD3_TCKDK_MIN_CYC" value="-0.27" />
|
|
<parameter name="MEM_RLD3_TCKQK_MAX_PS" value="135" />
|
|
<parameter name="MEM_RLD3_TDH_DC_MV" value="100" />
|
|
<parameter name="MEM_RLD3_TDH_PS" value="5" />
|
|
<parameter name="MEM_RLD3_TDS_AC_MV" value="150" />
|
|
<parameter name="MEM_RLD3_TDS_PS" value="-30" />
|
|
<parameter name="MEM_RLD3_TIH_DC_MV" value="100" />
|
|
<parameter name="MEM_RLD3_TIH_PS" value="65" />
|
|
<parameter name="MEM_RLD3_TIS_AC_MV" value="150" />
|
|
<parameter name="MEM_RLD3_TIS_PS" value="85" />
|
|
<parameter name="MEM_RLD3_TQH_CYC" value="0.38" />
|
|
<parameter name="MEM_RLD3_TQKQ_MAX_PS" value="75" />
|
|
<parameter name="MEM_RLD3_T_RC_MODE_ENUM" value="RLD3_TRC_9" />
|
|
<parameter name="MEM_RLD3_WIDTH_EXPANDED" value="false" />
|
|
<parameter name="MEM_RLD3_WRITE_PROTOCOL_ENUM" value="RLD3_WRITE_1BANK" />
|
|
<parameter name="PHY_DDR3_CAL_ADDR0" value="0" />
|
|
<parameter name="PHY_DDR3_CAL_ADDR1" value="8" />
|
|
<parameter name="PHY_DDR3_CAL_ENABLE_NON_DES" value="true" />
|
|
<parameter name="PHY_DDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
|
|
<parameter name="PHY_DDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
|
|
<parameter name="PHY_DDR3_DEFAULT_IO" value="true" />
|
|
<parameter name="PHY_DDR3_DEFAULT_REF_CLK_FREQ" value="false" />
|
|
<parameter name="PHY_DDR3_IO_VOLTAGE" value="1.5" />
|
|
<parameter name="PHY_DDR3_MEM_CLK_FREQ_MHZ" value="1066.667" />
|
|
<parameter name="PHY_DDR3_RATE_ENUM" value="RATE_HALF" />
|
|
<parameter name="PHY_DDR3_REF_CLK_JITTER_PS" value="10.0" />
|
|
<parameter name="PHY_DDR3_USER_AC_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_DDR3_USER_AC_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_DDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
|
|
<parameter name="PHY_DDR3_USER_CK_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_DDR3_USER_CK_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_DDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
|
|
<parameter name="PHY_DDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_DDR3_USER_DATA_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_DDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_DDR3_USER_PING_PONG_EN" value="false" />
|
|
<parameter name="PHY_DDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_DDR3_USER_REF_CLK_FREQ_MHZ" value="133.333" />
|
|
<parameter name="PHY_DDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_DDR4_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
|
|
<parameter name="PHY_DDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
|
|
<parameter name="PHY_DDR4_DEFAULT_IO" value="false" />
|
|
<parameter name="PHY_DDR4_DEFAULT_REF_CLK_FREQ" value="false" />
|
|
<parameter name="PHY_DDR4_IO_VOLTAGE" value="1.2" />
|
|
<parameter name="PHY_DDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
|
|
<parameter name="PHY_DDR4_RATE_ENUM" value="RATE_HALF" />
|
|
<parameter name="PHY_DDR4_REF_CLK_JITTER_PS" value="10.0" />
|
|
<parameter name="PHY_DDR4_STARTING_VREFIN" value="70.0" />
|
|
<parameter name="PHY_DDR4_USER_AC_IO_STD_ENUM" value="IO_STD_SSTL_12" />
|
|
<parameter name="PHY_DDR4_USER_AC_MODE_ENUM" value="OUT_OCT_40_CAL" />
|
|
<parameter name="PHY_DDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
|
|
<parameter name="PHY_DDR4_USER_CK_IO_STD_ENUM" value="IO_STD_SSTL_12" />
|
|
<parameter name="PHY_DDR4_USER_CK_MODE_ENUM" value="OUT_OCT_40_CAL" />
|
|
<parameter name="PHY_DDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
|
|
<parameter name="PHY_DDR4_USER_DATA_IN_MODE_ENUM" value="IN_OCT_60_CAL" />
|
|
<parameter name="PHY_DDR4_USER_DATA_IO_STD_ENUM" value="IO_STD_POD_12" />
|
|
<parameter name="PHY_DDR4_USER_DATA_OUT_MODE_ENUM" value="OUT_OCT_34_CAL" />
|
|
<parameter name="PHY_DDR4_USER_PING_PONG_EN" value="false" />
|
|
<parameter name="PHY_DDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="IO_STD_CMOS_12" />
|
|
<parameter name="PHY_DDR4_USER_REF_CLK_FREQ_MHZ" value="133.333" />
|
|
<parameter name="PHY_DDR4_USER_RZQ_IO_STD_ENUM" value="IO_STD_CMOS_12" />
|
|
<parameter name="PHY_LPDDR3_CONFIG_ENUM">CONFIG_PHY_AND_HARD_CTRL</parameter>
|
|
<parameter name="PHY_LPDDR3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
|
|
<parameter name="PHY_LPDDR3_DEFAULT_IO" value="true" />
|
|
<parameter name="PHY_LPDDR3_DEFAULT_REF_CLK_FREQ" value="true" />
|
|
<parameter name="PHY_LPDDR3_IO_VOLTAGE" value="1.2" />
|
|
<parameter name="PHY_LPDDR3_MEM_CLK_FREQ_MHZ" value="800.0" />
|
|
<parameter name="PHY_LPDDR3_RATE_ENUM" value="RATE_HALF" />
|
|
<parameter name="PHY_LPDDR3_REF_CLK_JITTER_PS" value="10.0" />
|
|
<parameter name="PHY_LPDDR3_USER_AC_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_LPDDR3_USER_AC_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_LPDDR3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
|
|
<parameter name="PHY_LPDDR3_USER_CK_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_LPDDR3_USER_CK_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_LPDDR3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
|
|
<parameter name="PHY_LPDDR3_USER_DATA_IN_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_LPDDR3_USER_DATA_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_LPDDR3_USER_DATA_OUT_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_LPDDR3_USER_PING_PONG_EN" value="false" />
|
|
<parameter name="PHY_LPDDR3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_LPDDR3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
|
|
<parameter name="PHY_LPDDR3_USER_RZQ_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_QDR2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
|
|
<parameter name="PHY_QDR2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
|
|
<parameter name="PHY_QDR2_DEFAULT_IO" value="true" />
|
|
<parameter name="PHY_QDR2_DEFAULT_REF_CLK_FREQ" value="true" />
|
|
<parameter name="PHY_QDR2_IO_VOLTAGE" value="1.5" />
|
|
<parameter name="PHY_QDR2_MEM_CLK_FREQ_MHZ" value="633.333" />
|
|
<parameter name="PHY_QDR2_RATE_ENUM" value="RATE_HALF" />
|
|
<parameter name="PHY_QDR2_REF_CLK_JITTER_PS" value="10.0" />
|
|
<parameter name="PHY_QDR2_USER_AC_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_QDR2_USER_AC_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_QDR2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
|
|
<parameter name="PHY_QDR2_USER_CK_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_QDR2_USER_CK_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_QDR2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
|
|
<parameter name="PHY_QDR2_USER_DATA_IN_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_QDR2_USER_DATA_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_QDR2_USER_DATA_OUT_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_QDR2_USER_PING_PONG_EN" value="false" />
|
|
<parameter name="PHY_QDR2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_QDR2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
|
|
<parameter name="PHY_QDR2_USER_RZQ_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_QDR4_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
|
|
<parameter name="PHY_QDR4_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
|
|
<parameter name="PHY_QDR4_DEFAULT_IO" value="true" />
|
|
<parameter name="PHY_QDR4_DEFAULT_REF_CLK_FREQ" value="true" />
|
|
<parameter name="PHY_QDR4_IO_VOLTAGE" value="1.2" />
|
|
<parameter name="PHY_QDR4_MEM_CLK_FREQ_MHZ" value="1066.667" />
|
|
<parameter name="PHY_QDR4_RATE_ENUM" value="RATE_QUARTER" />
|
|
<parameter name="PHY_QDR4_REF_CLK_JITTER_PS" value="10.0" />
|
|
<parameter name="PHY_QDR4_STARTING_VREFIN" value="70.0" />
|
|
<parameter name="PHY_QDR4_USER_AC_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_QDR4_USER_AC_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_QDR4_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
|
|
<parameter name="PHY_QDR4_USER_CK_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_QDR4_USER_CK_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_QDR4_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
|
|
<parameter name="PHY_QDR4_USER_DATA_IN_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_QDR4_USER_DATA_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_QDR4_USER_DATA_OUT_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_QDR4_USER_PING_PONG_EN" value="false" />
|
|
<parameter name="PHY_QDR4_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_QDR4_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
|
|
<parameter name="PHY_QDR4_USER_RZQ_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_RLD2_CONFIG_ENUM">CONFIG_PHY_AND_SOFT_CTRL</parameter>
|
|
<parameter name="PHY_RLD2_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
|
|
<parameter name="PHY_RLD2_DEFAULT_IO" value="true" />
|
|
<parameter name="PHY_RLD2_DEFAULT_REF_CLK_FREQ" value="true" />
|
|
<parameter name="PHY_RLD2_IO_VOLTAGE" value="1.8" />
|
|
<parameter name="PHY_RLD2_MEM_CLK_FREQ_MHZ" value="533.333" />
|
|
<parameter name="PHY_RLD2_RATE_ENUM" value="RATE_HALF" />
|
|
<parameter name="PHY_RLD2_REF_CLK_JITTER_PS" value="10.0" />
|
|
<parameter name="PHY_RLD2_USER_AC_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_RLD2_USER_AC_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_RLD2_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
|
|
<parameter name="PHY_RLD2_USER_CK_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_RLD2_USER_CK_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_RLD2_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
|
|
<parameter name="PHY_RLD2_USER_DATA_IN_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_RLD2_USER_DATA_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_RLD2_USER_DATA_OUT_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_RLD2_USER_PING_PONG_EN" value="false" />
|
|
<parameter name="PHY_RLD2_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_RLD2_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
|
|
<parameter name="PHY_RLD2_USER_RZQ_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_RLD3_CONFIG_ENUM" value="CONFIG_PHY_ONLY" />
|
|
<parameter name="PHY_RLD3_CORE_CLKS_SHARING_ENUM">CORE_CLKS_SHARING_DISABLED</parameter>
|
|
<parameter name="PHY_RLD3_DEFAULT_IO" value="true" />
|
|
<parameter name="PHY_RLD3_DEFAULT_REF_CLK_FREQ" value="true" />
|
|
<parameter name="PHY_RLD3_IO_VOLTAGE" value="1.2" />
|
|
<parameter name="PHY_RLD3_MEM_CLK_FREQ_MHZ" value="1066.667" />
|
|
<parameter name="PHY_RLD3_RATE_ENUM" value="RATE_QUARTER" />
|
|
<parameter name="PHY_RLD3_REF_CLK_JITTER_PS" value="10.0" />
|
|
<parameter name="PHY_RLD3_USER_AC_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_RLD3_USER_AC_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_RLD3_USER_AC_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
|
|
<parameter name="PHY_RLD3_USER_CK_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_RLD3_USER_CK_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_RLD3_USER_CK_SLEW_RATE_ENUM" value="SLEW_RATE_FAST" />
|
|
<parameter name="PHY_RLD3_USER_DATA_IN_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_RLD3_USER_DATA_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_RLD3_USER_DATA_OUT_MODE_ENUM" value="unset" />
|
|
<parameter name="PHY_RLD3_USER_PING_PONG_EN" value="false" />
|
|
<parameter name="PHY_RLD3_USER_PLL_REF_CLK_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PHY_RLD3_USER_REF_CLK_FREQ_MHZ" value="-1.0" />
|
|
<parameter name="PHY_RLD3_USER_RZQ_IO_STD_ENUM" value="unset" />
|
|
<parameter name="PLL_ADD_EXTRA_CLKS" value="0" />
|
|
<parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_5" value="50.0" />
|
|
<parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_6" value="50.0" />
|
|
<parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_7" value="50.0" />
|
|
<parameter name="PLL_EXTRA_CLK_ACTUAL_DUTY_CYCLE_GUI_8" value="50.0" />
|
|
<parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_5" value="100.0" />
|
|
<parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_6" value="100.0" />
|
|
<parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_7" value="100.0" />
|
|
<parameter name="PLL_EXTRA_CLK_ACTUAL_FREQ_MHZ_GUI_8" value="100.0" />
|
|
<parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_5" value="0.0" />
|
|
<parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_6" value="0.0" />
|
|
<parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_7" value="0.0" />
|
|
<parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_DEG_GUI_8" value="0.0" />
|
|
<parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_5" value="0.0" />
|
|
<parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_6" value="0.0" />
|
|
<parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_7" value="0.0" />
|
|
<parameter name="PLL_EXTRA_CLK_ACTUAL_PHASE_PS_GUI_8" value="0.0" />
|
|
<parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_5" value="50.0" />
|
|
<parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_6" value="50.0" />
|
|
<parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_7" value="50.0" />
|
|
<parameter name="PLL_EXTRA_CLK_DESIRED_DUTY_CYCLE_GUI_8" value="50.0" />
|
|
<parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_5" value="100.0" />
|
|
<parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_6" value="100.0" />
|
|
<parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_7" value="100.0" />
|
|
<parameter name="PLL_EXTRA_CLK_DESIRED_FREQ_MHZ_GUI_8" value="100.0" />
|
|
<parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_5" value="0.0" />
|
|
<parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_6" value="0.0" />
|
|
<parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_7" value="0.0" />
|
|
<parameter name="PLL_EXTRA_CLK_DESIRED_PHASE_GUI_8" value="0.0" />
|
|
<parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_0" value="0" />
|
|
<parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_1" value="0" />
|
|
<parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_2" value="0" />
|
|
<parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_3" value="0" />
|
|
<parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_4" value="0" />
|
|
<parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_5" value="0" />
|
|
<parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_6" value="0" />
|
|
<parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_7" value="0" />
|
|
<parameter name="PLL_EXTRA_CLK_PHASE_SHIFT_UNIT_GUI_8" value="0" />
|
|
<parameter name="PLL_USER_NUM_OF_EXTRA_CLKS" value="0" />
|
|
<parameter name="PROTOCOL_ENUM" value="PROTOCOL_DDR4" />
|
|
<parameter name="SHORT_QSYS_INTERFACE_NAMES" value="false" />
|
|
<parameter name="SYS_INFO_DEVICE" value="10AS066N3F40I2SGES" />
|
|
<parameter name="SYS_INFO_DEVICE_FAMILY" value="Arria 10" />
|
|
<parameter name="SYS_INFO_DEVICE_SPEEDGRADE" value="2" />
|
|
<parameter name="SYS_INFO_UNIQUE_ID">$${FILENAME}_emif_a10_hps_0</parameter>
|
|
<parameter name="TRAIT_SUPPORTS_VID" value="0" />
|
|
</module>
|
|
<module name="sys_clk" kind="altera_clock_bridge" version="15.1" enabled="1">
|
|
<parameter name="DERIVED_CLOCK_RATE" value="0" />
|
|
<parameter name="EXPLICIT_CLOCK_RATE" value="100000000" />
|
|
<parameter name="NUM_CLOCK_OUTPUTS" value="1" />
|
|
</module>
|
|
<module
|
|
name="sys_cpu_interconnect"
|
|
kind="altera_avalon_mm_bridge"
|
|
version="15.1"
|
|
enabled="1">
|
|
<parameter name="ADDRESS_UNITS" value="SYMBOLS" />
|
|
<parameter name="ADDRESS_WIDTH" value="32" />
|
|
<parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
|
|
<parameter name="AUTO_DEVICE_FAMILY" value="Arria 10" />
|
|
<parameter name="DATA_WIDTH" value="32" />
|
|
<parameter name="LINEWRAPBURSTS" value="0" />
|
|
<parameter name="MAX_BURST_SIZE" value="1" />
|
|
<parameter name="MAX_PENDING_RESPONSES" value="4" />
|
|
<parameter name="PIPELINE_COMMAND" value="1" />
|
|
<parameter name="PIPELINE_RESPONSE" value="1" />
|
|
<parameter name="SYMBOL_WIDTH" value="8" />
|
|
<parameter name="SYSINFO_ADDR_WIDTH" value="10" />
|
|
<parameter name="USE_AUTO_ADDRESS_WIDTH" value="1" />
|
|
<parameter name="USE_RESPONSE" value="0" />
|
|
</module>
|
|
<module name="sys_rst" kind="altera_reset_bridge" version="15.1" enabled="1">
|
|
<parameter name="ACTIVE_LOW_RESET" value="0" />
|
|
<parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
|
|
<parameter name="NUM_RESET_OUTPUTS" value="1" />
|
|
<parameter name="SYNCHRONOUS_EDGES" value="deassert" />
|
|
<parameter name="USE_RESET_REQUEST" value="0" />
|
|
</module>
|
|
<module
|
|
name="sys_rst_in"
|
|
kind="altera_reset_bridge"
|
|
version="15.1"
|
|
enabled="1">
|
|
<parameter name="ACTIVE_LOW_RESET" value="0" />
|
|
<parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
|
|
<parameter name="NUM_RESET_OUTPUTS" value="1" />
|
|
<parameter name="SYNCHRONOUS_EDGES" value="deassert" />
|
|
<parameter name="USE_RESET_REQUEST" value="0" />
|
|
</module>
|
|
<connection
|
|
kind="avalon"
|
|
version="15.1"
|
|
start="arria10_hps_0.h2f_lw_axi_master"
|
|
end="sys_cpu_interconnect.s0">
|
|
<parameter name="arbitrationPriority" value="1" />
|
|
<parameter name="baseAddress" value="0x0000" />
|
|
<parameter name="defaultConnection" value="false" />
|
|
</connection>
|
|
<connection
|
|
kind="clock"
|
|
version="15.1"
|
|
start="sys_clk.out_clk"
|
|
end="sys_rst_in.clk" />
|
|
<connection
|
|
kind="clock"
|
|
version="15.1"
|
|
start="sys_clk.out_clk"
|
|
end="sys_cpu_interconnect.clk" />
|
|
<connection kind="clock" version="15.1" start="sys_clk.out_clk" end="sys_rst.clk" />
|
|
<connection
|
|
kind="clock"
|
|
version="15.1"
|
|
start="sys_clk.out_clk"
|
|
end="arria10_hps_0.f2sdram1_clock" />
|
|
<connection
|
|
kind="clock"
|
|
version="15.1"
|
|
start="sys_clk.out_clk"
|
|
end="arria10_hps_0.h2f_lw_axi_clock" />
|
|
<connection
|
|
kind="conduit"
|
|
version="15.1"
|
|
start="emif_a10_hps_0.hps_emif_conduit_end"
|
|
end="arria10_hps_0.emif">
|
|
<parameter name="endPort" value="" />
|
|
<parameter name="endPortLSB" value="0" />
|
|
<parameter name="startPort" value="" />
|
|
<parameter name="startPortLSB" value="0" />
|
|
<parameter name="width" value="0" />
|
|
</connection>
|
|
<connection
|
|
kind="reset"
|
|
version="15.1"
|
|
start="arria10_hps_0.h2f_reset"
|
|
end="sys_rst.in_reset" />
|
|
<connection
|
|
kind="reset"
|
|
version="15.1"
|
|
start="sys_rst_in.out_reset"
|
|
end="arria10_hps_0.f2h_cold_reset_req" />
|
|
<connection
|
|
kind="reset"
|
|
version="15.1"
|
|
start="sys_rst_in.out_reset"
|
|
end="emif_a10_hps_0.global_reset_reset_sink" />
|
|
<connection
|
|
kind="reset"
|
|
version="15.1"
|
|
start="sys_rst_in.out_reset"
|
|
end="sys_rst.in_reset" />
|
|
<connection
|
|
kind="reset"
|
|
version="15.1"
|
|
start="sys_rst_in.out_reset"
|
|
end="sys_cpu_interconnect.reset" />
|
|
<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="FIFO" />
|
|
<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="false" />
|
|
<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="2" />
|
|
</system>
|