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AndreiGrozav cde9956948 ad4858_fmcz: Initial design 
Reference design for AD4858 20-bit, low noise 8-channel, SAR ADC with
buffered differential, wide common range picoamp inputs.

The design supports:
- CMOS and LVDS interfaces(at build time)
- Runtime sampling changes
- Store captured samples in RAM, through DMA (available via software support)

Documentation at: https://wiki.analog.com/resources/eval/user-guides/ad4858_fmcz/ad4858_fmcz_hdl
 		2023-10-05 10:19:03 +03:00
..
Makefile ad4858_fmcz: Initial design 2023-10-05 10:19:03 +03:00
README.rst ad4858_fmcz: Initial design 2023-10-05 10:19:03 +03:00
system_bd.tcl ad4858_fmcz: Initial design 2023-10-05 10:19:03 +03:00
system_constr.tcl ad4858_fmcz: Initial design 2023-10-05 10:19:03 +03:00
system_project.tcl ad4858_fmcz: Initial design 2023-10-05 10:19:03 +03:00
system_top_cmos.v ad4858_fmcz: Initial design 2023-10-05 10:19:03 +03:00
system_top_lvds.v ad4858_fmcz: Initial design 2023-10-05 10:19:03 +03:00

README.rst 

- Connect on FMC LPC
- VADJ = 1.8V to 3.3V
Make sure that all power supply source/voltage selection jumpers are
properly placed according to your use case on both the eval board and zed.

The default interface at build is CMOS. To explicitly select an interface:

- make LVDS_CMOS_N=0 for CMOS interface
- make LVDS_CMOS_N=1 for LVDS interface