128 lines
5.2 KiB
Tcl
128 lines
5.2 KiB
Tcl
###############################################################################
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## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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#
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# Parameter description:
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# RX_JESD_M : Number of converters per link
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# RX_JESD_L : Number of lanes per link
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# RX_JESD_S : Number of samples per frame
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# RX_JESD_NP : Number of bits per sample
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#
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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# JESD204B interface configuration parameters
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set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L)
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set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M)
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set RX_SAMPLES_PER_FRAME $ad_project_params(RX_JESD_S)
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set RX_SAMPLE_WIDTH $ad_project_params(RX_JESD_NP)
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set adc_fifo_name axi_ad9625_fifo
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set adc_data_width [expr 32*$RX_NUM_OF_LANES]
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set adc_dma_data_width 64
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# adc peripherals
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adi_tpl_jesd204_rx_create axi_ad9625_core $RX_NUM_OF_LANES \
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$RX_NUM_OF_CONVERTERS \
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$RX_SAMPLES_PER_FRAME \
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$RX_SAMPLE_WIDTH \
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adi_axi_jesd204_rx_create axi_ad9625_jesd $RX_NUM_OF_LANES
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ad_ip_instance axi_adxcvr axi_ad9625_xcvr
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ad_ip_parameter axi_ad9625_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
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ad_ip_parameter axi_ad9625_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_ad9625_xcvr CONFIG.TX_OR_RX_N 0
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ad_ip_parameter axi_ad9625_xcvr CONFIG.LPM_OR_DFE_N 1
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ad_ip_parameter axi_ad9625_xcvr CONFIG.SYS_CLK_SEL 0
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ad_ip_parameter axi_ad9625_xcvr CONFIG.OUT_CLK_SEL 2
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ad_ip_instance axi_dmac axi_ad9625_dma
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ad_ip_parameter axi_ad9625_dma CONFIG.DMA_TYPE_SRC 1
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ad_ip_parameter axi_ad9625_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_ad9625_dma CONFIG.ID 0
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ad_ip_parameter axi_ad9625_dma CONFIG.AXI_SLICE_SRC 0
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ad_ip_parameter axi_ad9625_dma CONFIG.AXI_SLICE_DEST 0
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ad_ip_parameter axi_ad9625_dma CONFIG.SYNC_TRANSFER_START 0
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ad_ip_parameter axi_ad9625_dma CONFIG.DMA_LENGTH_WIDTH 24
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ad_ip_parameter axi_ad9625_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_ad9625_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_ad9625_dma CONFIG.DMA_DATA_WIDTH_SRC 64
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ad_ip_parameter axi_ad9625_dma CONFIG.DMA_DATA_WIDTH_DEST 64
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ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_dma_data_width $adc_fifo_address_width
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ad_ip_instance util_adxcvr util_fmcadc2_xcvr
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ad_ip_parameter util_fmcadc2_xcvr CONFIG.QPLL_FBDIV 0x80 ;# N = 40
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ad_ip_parameter util_fmcadc2_xcvr CONFIG.CPLL_FBDIV 1
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ad_ip_parameter util_fmcadc2_xcvr CONFIG.TX_NUM_OF_LANES 0
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ad_ip_parameter util_fmcadc2_xcvr CONFIG.RX_NUM_OF_LANES $RX_NUM_OF_LANES
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ad_ip_parameter util_fmcadc2_xcvr CONFIG.RX_OUT_DIV 1
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ad_ip_parameter util_fmcadc2_xcvr CONFIG.RX_CLK25_DIV 25
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ad_ip_parameter util_fmcadc2_xcvr CONFIG.RX_DFE_LPM_CFG 0x0904
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ad_ip_parameter util_fmcadc2_xcvr CONFIG.RX_CDR_CFG 0x03000023ff20400020 ;# DFE mode refclk +-200
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# reference clocks & resets
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create_bd_port -dir I rx_ref_clk_0
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create_bd_port -dir O rx_core_clk
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ad_xcvrpll rx_ref_clk_0 util_fmcadc2_xcvr/qpll_ref_clk_*
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ad_xcvrpll rx_ref_clk_0 util_fmcadc2_xcvr/cpll_ref_clk_*
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ad_xcvrpll axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_qpll_rst_*
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ad_xcvrpll axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_cpll_rst_*
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ad_connect $sys_cpu_resetn util_fmcadc2_xcvr/up_rstn
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ad_connect $sys_cpu_clk util_fmcadc2_xcvr/up_clk
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# connections (adc)
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ad_xcvrcon util_fmcadc2_xcvr axi_ad9625_xcvr axi_ad9625_jesd
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ad_connect util_fmcadc2_xcvr/rx_out_clk_0 axi_ad9625_core/link_clk
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ad_connect rx_core_clk util_fmcadc2_xcvr/rx_out_clk_0
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ad_connect axi_ad9625_jesd/rx_data_tdata axi_ad9625_core/link_data
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ad_connect axi_ad9625_jesd/rx_sof axi_ad9625_core/link_sof
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ad_connect axi_ad9625_jesd/rx_data_tvalid axi_ad9625_core/link_valid
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ad_connect $sys_cpu_clk axi_ad9625_fifo/dma_clk
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ad_connect $sys_cpu_clk axi_ad9625_dma/s_axis_aclk
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ad_connect $sys_cpu_resetn axi_ad9625_dma/m_dest_axi_aresetn
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ad_connect axi_ad9625_core/link_clk axi_ad9625_fifo/adc_clk
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ad_connect axi_ad9625_jesd_rstgen/peripheral_reset axi_ad9625_fifo/adc_rst
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ad_connect axi_ad9625_core/adc_enable_0 axi_ad9625_fifo/adc_wr
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ad_connect axi_ad9625_core/adc_data_0 axi_ad9625_fifo/adc_wdata
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ad_connect axi_ad9625_core/adc_dovf axi_ad9625_fifo/adc_wovf
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ad_connect axi_ad9625_fifo/dma_wr axi_ad9625_dma/s_axis_valid
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ad_connect axi_ad9625_fifo/dma_wdata axi_ad9625_dma/s_axis_data
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ad_connect axi_ad9625_fifo/dma_wready axi_ad9625_dma/s_axis_ready
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ad_connect axi_ad9625_fifo/dma_xfer_req axi_ad9625_dma/s_axis_xfer_req
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# interconnect (cpu)
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ad_cpu_interconnect 0x44A60000 axi_ad9625_xcvr
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ad_cpu_interconnect 0x44A10000 axi_ad9625_core
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ad_cpu_interconnect 0x44AA0000 axi_ad9625_jesd
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ad_cpu_interconnect 0x7c420000 axi_ad9625_dma
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# gt uses hp3, and 100MHz clock for both DRP and AXI4
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ad_mem_hp3_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect $sys_cpu_clk axi_ad9625_xcvr/m_axi
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# interconnect (mem/adc)
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ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2
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ad_mem_hp2_interconnect $sys_cpu_clk axi_ad9625_dma/m_dest_axi
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# interrupts
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ad_cpu_interrupt ps-12 mb-13 axi_ad9625_jesd/irq
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ad_cpu_interrupt ps-13 mb-12 axi_ad9625_dma/irq
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# Create dummy outputs for unused Rx lanes
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for {set i $RX_NUM_OF_LANES} {$i < 8} {incr i} {
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create_bd_port -dir I rx_data_${i}_n
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create_bd_port -dir I rx_data_${i}_p
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}
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