59 lines
1.9 KiB
Verilog
59 lines
1.9 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
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//
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// Each core or library found in this collection may have its own licensing terms.
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// The user should keep this in in mind while exploring these cores.
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//
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// Redistribution and use in source and binary forms,
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// with or without modification of this file, are permitted under the terms of either
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// (at the option of the user):
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory, or at:
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// https://www.gnu.org/licenses/old-licenses/gpl-2.0.en.html
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//
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// OR
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//
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// 2. An ADI specific BSD license as noted in the top level directory, or on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/dev/LICENSE
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//
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/1ns
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module qpsk_mod (
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input clk,
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input [ 1:0] data_input,
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input data_valid,
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output [15:0] data_qpsk_i,
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output [15:0] data_qpsk_q);
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wire [15:0] modulated_data_i;
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wire [15:0] modulated_data_q;
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wire [15:0] filtered_data_i;
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wire [15:0] filtered_data_q;
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// output logic
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assign data_qpsk_i = filtered_data_i;
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assign data_qpsk_q = filtered_data_q;
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// instantiations
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QPSK_Modulator_Baseband i_qpsk_mod (
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.in0({6'b0, data_input}),
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.out0_re(modulated_data_i),
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.out0_im(modulated_data_q)
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);
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Raised_Cosine_Transmit_Filter i_tx_filter (
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.clk(clk),
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.reset(),
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.enb_1_1_1(data_valid),
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.In1_re(modulated_data_i),
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.In1_im(modulated_data_q),
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.Out1_re(filtered_data_i),
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.Out1_im(filtered_data_q)
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);
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endmodule
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