98 lines
2.8 KiB
Verilog
98 lines
2.8 KiB
Verilog
// ***************************************************************************
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// ***************************************************************************
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// Copyright 2018 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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// developed independently, and may be accompanied by separate and unique license
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// terms.
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//
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// The user should read each of these license terms, and understand the
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// freedoms and responsibilities that he or she has by using this source/core.
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//
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// This core is distributed in the hope that it will be useful, but WITHOUT ANY
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// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
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// A PARTICULAR PURPOSE.
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//
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// Redistribution and use of source or resulting binaries, with or without modification
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// of this file, are permitted under one of the following two license terms:
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//
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// 1. The GNU General Public License version 2 as published by the
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// Free Software Foundation, which can be found in the top level directory
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// of this repository (LICENSE_GPL2), and also online at:
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// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
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//
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// OR
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//
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// 2. An ADI specific BSD license, which can be found in the top level directory
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// of this repository (LICENSE_ADIBSD), and also on-line at:
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// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
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// This will allow to generate bit files and not release the source code,
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// as long as it attaches to an ADI device.
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//
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// ***************************************************************************
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// ***************************************************************************
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module axi_read_slave #(
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parameter DATA_WIDTH = 32,
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parameter READ_ACCEPTANCE = 4,
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parameter MIN_LATENCY = 48,
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parameter MAX_LATENCY = 48
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) (
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input clk,
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input reset,
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input arvalid,
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output arready,
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input [31:0] araddr,
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input [7:0] arlen,
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input [2:0] arsize,
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input [1:0] arburst,
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input [2:0] arprot,
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input [3:0] arcache,
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output rvalid,
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input rready,
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output [DATA_WIDTH-1:0] rdata,
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output [1:0] rresp,
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output rlast
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);
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reg [DATA_WIDTH-1:0] data = 'h00;
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assign rresp = 2'b00;
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//assign rdata = data;
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always @(posedge clk) begin
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if (reset == 1'b1) begin
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data <= 'h00;
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end else if (rvalid == 1'b1 && rready == 1'b1) begin
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data <= data + 1'b1;
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end
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end
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axi_slave #(
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.ACCEPTANCE(READ_ACCEPTANCE),
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.MIN_LATENCY(MIN_LATENCY),
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.MAX_LATENCY(MAX_LATENCY)
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) i_axi_slave (
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.clk(clk),
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.reset(reset),
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.valid(arvalid),
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.ready(arready),
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.addr(araddr),
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.len(arlen),
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.size(arsize),
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.burst(arburst),
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.prot(arprot),
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.cache(arcache),
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.beat_stb(rvalid),
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.beat_ack(rvalid & rready),
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.beat_last(rlast),
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.beat_addr(rdata)
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);
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endmodule
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