88 lines
5.0 KiB
Plaintext
88 lines
5.0 KiB
Plaintext
###############################################################################
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## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# constraints
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set_property -dict {PACKAGE_PIN AV40 IOSTANDARD LVCMOS18} [get_ports sys_rst]
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# clocks
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set_property -dict {PACKAGE_PIN E19 IOSTANDARD LVDS} [get_ports sys_clk_p]
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set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS} [get_ports sys_clk_n]
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# ethernet
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set_property PACKAGE_PIN AN2 [get_ports sgmii_txp]
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set_property PACKAGE_PIN AN1 [get_ports sgmii_txn]
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set_property PACKAGE_PIN AM8 [get_ports sgmii_rxp]
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set_property PACKAGE_PIN AM7 [get_ports sgmii_rxn]
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set_property PACKAGE_PIN AH8 [get_ports mgt_clk_p]
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set_property PACKAGE_PIN AH7 [get_ports mgt_clk_n]
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# Define the 125 MHz SGMII clock
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create_clock -name mgt_clk -period 8.00 [get_ports mgt_clk_p]
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set_property -dict {PACKAGE_PIN AJ33 IOSTANDARD LVCMOS18} [get_ports phy_rstn]
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set_property -dict {PACKAGE_PIN AH31 IOSTANDARD LVCMOS18} [get_ports mdio_mdc]
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set_property -dict {PACKAGE_PIN AK33 IOSTANDARD LVCMOS18} [get_ports mdio_mdio]
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set_false_path -through [get_nets phy_rstn]
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# uart
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set_property -dict {PACKAGE_PIN AU33 IOSTANDARD LVCMOS18} [get_ports uart_sin]
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set_property -dict {PACKAGE_PIN AU36 IOSTANDARD LVCMOS18} [get_ports uart_sout]
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# fan
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set_property -dict {PACKAGE_PIN BA37 IOSTANDARD LVCMOS18} [get_ports fan_pwm]
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# lcd
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set_property -dict {PACKAGE_PIN AT40 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[6]] ; ## lcd_e
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set_property -dict {PACKAGE_PIN AN41 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[5]] ; ## lcd_rs
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set_property -dict {PACKAGE_PIN AR42 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[4]] ; ## lcd_rw
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set_property -dict {PACKAGE_PIN AN40 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[3]] ; ## lcd_db[7]
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set_property -dict {PACKAGE_PIN AR39 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[2]] ; ## lcd_db[6]
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set_property -dict {PACKAGE_PIN AR38 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[1]] ; ## lcd_db[5]
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set_property -dict {PACKAGE_PIN AT42 IOSTANDARD LVCMOS18} [get_ports gpio_lcd[0]] ; ## lcd_db[4]
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set_property -dict {PACKAGE_PIN AV30 IOSTANDARD LVCMOS18} [get_ports gpio_bd[0]] ; ## GPIO_DIP_SW0
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set_property -dict {PACKAGE_PIN AY33 IOSTANDARD LVCMOS18} [get_ports gpio_bd[1]] ; ## GPIO_DIP_SW1
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set_property -dict {PACKAGE_PIN BA31 IOSTANDARD LVCMOS18} [get_ports gpio_bd[2]] ; ## GPIO_DIP_SW2
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set_property -dict {PACKAGE_PIN BA32 IOSTANDARD LVCMOS18} [get_ports gpio_bd[3]] ; ## GPIO_DIP_SW3
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set_property -dict {PACKAGE_PIN AW30 IOSTANDARD LVCMOS18} [get_ports gpio_bd[4]] ; ## GPIO_DIP_SW4
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set_property -dict {PACKAGE_PIN AY30 IOSTANDARD LVCMOS18} [get_ports gpio_bd[5]] ; ## GPIO_DIP_SW5
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set_property -dict {PACKAGE_PIN BA30 IOSTANDARD LVCMOS18} [get_ports gpio_bd[6]] ; ## GPIO_DIP_SW6
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set_property -dict {PACKAGE_PIN BB31 IOSTANDARD LVCMOS18} [get_ports gpio_bd[7]] ; ## GPIO_DIP_SW7
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set_property -dict {PACKAGE_PIN AR40 IOSTANDARD LVCMOS18} [get_ports gpio_bd[8]] ; ## GPIO_SW_N
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set_property -dict {PACKAGE_PIN AU38 IOSTANDARD LVCMOS18} [get_ports gpio_bd[9]] ; ## GPIO_SW_E
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set_property -dict {PACKAGE_PIN AP40 IOSTANDARD LVCMOS18} [get_ports gpio_bd[10]] ; ## GPIO_SW_S
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set_property -dict {PACKAGE_PIN AW40 IOSTANDARD LVCMOS18} [get_ports gpio_bd[11]] ; ## GPIO_SW_W
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set_property -dict {PACKAGE_PIN AV39 IOSTANDARD LVCMOS18} [get_ports gpio_bd[12]] ; ## GPIO_SW_C
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set_property -dict {PACKAGE_PIN AM39 IOSTANDARD LVCMOS18} [get_ports gpio_bd[13]] ; ## GPIO_LED_0_LS
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set_property -dict {PACKAGE_PIN AN39 IOSTANDARD LVCMOS18} [get_ports gpio_bd[14]] ; ## GPIO_LED_1_LS
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set_property -dict {PACKAGE_PIN AR37 IOSTANDARD LVCMOS18} [get_ports gpio_bd[15]] ; ## GPIO_LED_2_LS
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set_property -dict {PACKAGE_PIN AT37 IOSTANDARD LVCMOS18} [get_ports gpio_bd[16]] ; ## GPIO_LED_3_LS
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set_property -dict {PACKAGE_PIN AR35 IOSTANDARD LVCMOS18} [get_ports gpio_bd[17]] ; ## GPIO_LED_4_LS
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set_property -dict {PACKAGE_PIN AP41 IOSTANDARD LVCMOS18} [get_ports gpio_bd[18]] ; ## GPIO_LED_5_LS
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set_property -dict {PACKAGE_PIN AP42 IOSTANDARD LVCMOS18} [get_ports gpio_bd[19]] ; ## GPIO_LED_6_LS
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set_property -dict {PACKAGE_PIN AU39 IOSTANDARD LVCMOS18} [get_ports gpio_bd[20]] ; ## GPIO_LED_7_LS
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# iic
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set_property -dict {PACKAGE_PIN AY42 IOSTANDARD LVCMOS18} [get_ports iic_rstn]
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set_property -dict {PACKAGE_PIN AT35 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_scl]
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set_property -dict {PACKAGE_PIN AU32 IOSTANDARD LVCMOS18 DRIVE 8 SLEW SLOW} [get_ports iic_sda]
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#Setting the Configuration Bank Voltage Select
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set_property CFGBVS GND [current_design]
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set_property CONFIG_VOLTAGE 1.8 [current_design]
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# Create SPI clock
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create_generated_clock -name spi_clk \
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-source [get_pins i_system_wrapper/system_i/axi_spi/ext_spi_clk] \
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-divide_by 2 [get_pins i_system_wrapper/system_i/axi_spi/sck_o]
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